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Commit 8ab43976 authored by Jesse Barnes's avatar Jesse Barnes Committed by Daniel Vetter
Browse files

drm/i915: implement WaDisableDopClockGatingisable on VLV and IVB

v2: use correct register
v3: remove extra hunks, pull in register definitions & offset check directly
v4: add GT1 vs GT2 distinction for IVB portion (Ben)

References: https://bugs.freedesktop.org/show_bug.cgi?id=50233


Reviewed-by: default avatarBen Widawsky <ben@bwidawsk.net>
Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: default avatarAntti Koskipää <antti.koskipaa@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent d0cf5ead
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+7 −0
Original line number Diff line number Diff line
@@ -1132,6 +1132,13 @@ static bool IS_DISPLAYREG(u32 reg)
	if (reg == GEN6_GDRST)
		return false;

	switch (reg) {
	case GEN7_ROW_CHICKEN2:
		return false;
	default:
		break;
	}

	return true;
}

+3 −0
Original line number Diff line number Diff line
@@ -1125,6 +1125,9 @@ struct drm_i915_file_private {
#define IS_IRONLAKE_D(dev)	((dev)->pci_device == 0x0042)
#define IS_IRONLAKE_M(dev)	((dev)->pci_device == 0x0046)
#define IS_IVYBRIDGE(dev)	(INTEL_INFO(dev)->is_ivybridge)
#define IS_IVB_GT1(dev)		((dev)->pci_device == 0x0156 || \
				 (dev)->pci_device == 0x0152 ||	\
				 (dev)->pci_device == 0x015a)
#define IS_VALLEYVIEW(dev)	(INTEL_INFO(dev)->is_valleyview)
#define IS_HASWELL(dev)	(INTEL_INFO(dev)->is_haswell)
#define IS_MOBILE(dev)		(INTEL_INFO(dev)->is_mobile)
+4 −0
Original line number Diff line number Diff line
@@ -4303,6 +4303,10 @@
#define GEN7_L3LOG_BASE			0xB070
#define GEN7_L3LOG_SIZE			0x80

#define GEN7_ROW_CHICKEN2		0xe4f4
#define GEN7_ROW_CHICKEN2_GT2		0xf4f4
#define   DOP_CLOCK_GATING_DISABLE	(1<<0)

#define G4X_AUD_VID_DID			0x62020
#define INTEL_AUDIO_DEVCL		0x808629FB
#define INTEL_AUDIO_DEVBLC		0x80862801
+12 −1
Original line number Diff line number Diff line
@@ -3601,6 +3601,13 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
			GEN7_WA_FOR_GEN7_L3_CONTROL);
	I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
		   GEN7_WA_L3_CHICKEN_MODE);
	if (IS_IVB_GT1(dev))
		I915_WRITE(GEN7_ROW_CHICKEN2,
			   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
	else
		I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
			   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));


	/* WaForceL3Serialization */
	I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
@@ -3684,6 +3691,10 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
	I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
		   ~L3SQ_URB_READ_CAM_MATCH_DISABLE);

	/* WaDisableDopClockGating */
	I915_WRITE(GEN7_ROW_CHICKEN2,
		   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));

	/* This is required by WaCatErrorRejectionIssue */
	I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
		   I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |