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Commit d0cf5ead authored by Jesse Barnes's avatar Jesse Barnes Committed by Daniel Vetter
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drm/i915: implement WaDisableL3CacheAging on VLV 



Needs to be set on every context restore as well, so set it as part of
the initial state so we can save/restore it.  Note this removes the IVB
workaround value from VLV and uses the default value, just adding in the
L3 cache aging disable bit, since the IVB value is wrong for VLV.

Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: default avatarAntti Koskipää <antti.koskipaa@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 1ad960f2

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -3470,6 +3470,7 @@ 


#define GEN7_L3CNTLREG1				0xB01C

#define  GEN7_WA_FOR_GEN7_L3_CONTROL			0x3C4FFF8C

#define  GEN7_L3AGDIS				(1<<19)



#define GEN7_L3_CHICKEN_MODE_REGISTER		0xB030

#define  GEN7_WA_L3_CHICKEN_MODE				0x20000000

drivers/gpu/drm/i915/intel_pm.c

+1 −1
Original line number Diff line number Diff line
@@ -3677,7 +3677,7 @@ static void valleyview_init_clock_gating(struct drm_device *dev) 
		   GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);



	/* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */

	I915_WRITE(GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL);

	I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);

	I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);



	/* WaForceL3Serialization */