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Commit 888510f4 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: separate jtagv8-mm device tree changes for msm8996"

parents 14c05b7a 04a4c1d9

arch/arm/boot/dts/qcom/msm8996-v2.dtsi

+52 −0
Original line number Diff line number Diff line
@@ -581,6 +581,58 @@ 
			qcom,levels = <4 5 5>; /* Nominal, Turbo, Turbo */

		};

	};



	jtag_mm0: jtagmm@3840000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x3840000 0x1000>;

		reg-names = "etm-base";



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";



		qcom,coresight-jtagmm-cpu = <&CPU0>;

		qcom,si-enable;

	};



	jtag_mm1: jtagmm@3940000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x3940000 0x1000>;

		reg-names = "etm-base";



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";



		qcom,coresight-jtagmm-cpu = <&CPU1>;

		qcom,si-enable;

	};



	jtag_mm2: jtagmm@3a40000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x3a40000 0x1000>;

		reg-names = "etm-base";



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";



		qcom,coresight-jtagmm-cpu = <&CPU2>;

		qcom,si-enable;

	};



	jtag_mm3: jtagmm@3b40000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x3b40000 0x1000>;

		reg-names = "etm-base";



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";



		qcom,coresight-jtagmm-cpu = <&CPU3>;

		qcom,si-enable;

	};

};



&tsens0 {

arch/arm/boot/dts/qcom/msm8996-v3.dtsi

+50 −0
Original line number Diff line number Diff line
@@ -167,6 +167,56 @@ 
	};

};



&soc {

	jtag_mm0: jtagmm@3840000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x3840000 0x1000>;

		reg-names = "etm-base";



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";



		qcom,coresight-jtagmm-cpu = <&CPU0>;

	};



	jtag_mm1: jtagmm@3940000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x3940000 0x1000>;

		reg-names = "etm-base";



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";



		qcom,coresight-jtagmm-cpu = <&CPU1>;

	};



	jtag_mm2: jtagmm@3a40000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x3a40000 0x1000>;

		reg-names = "etm-base";



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";



		qcom,coresight-jtagmm-cpu = <&CPU2>;

	};



	jtag_mm3: jtagmm@3b40000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x3b40000 0x1000>;

		reg-names = "etm-base";



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";



		qcom,coresight-jtagmm-cpu = <&CPU3>;

	};

};



&mdss_hdmi_pll {

	compatible = "qcom,mdss_hdmi_pll_8996_v3";

};

arch/arm/boot/dts/qcom/msm8996.dtsi

+0 −52
Original line number Diff line number Diff line
@@ -1941,58 +1941,6 @@ 
		reg-names = "fuse-base";

	};



	jtag_mm0: jtagmm@3840000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x3840000 0x1000>;

		reg-names = "etm-base";



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";



		qcom,coresight-jtagmm-cpu = <&CPU0>;

		qcom,si-enable;

	};



	jtag_mm1: jtagmm@3940000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x3940000 0x1000>;

		reg-names = "etm-base";



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";



		qcom,coresight-jtagmm-cpu = <&CPU1>;

		qcom,si-enable;

	};



	jtag_mm2: jtagmm@3a40000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x3a40000 0x1000>;

		reg-names = "etm-base";



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";



		qcom,coresight-jtagmm-cpu = <&CPU2>;

		qcom,si-enable;

	};



	jtag_mm3: jtagmm@3b40000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x3b40000 0x1000>;

		reg-names = "etm-base";



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";



		qcom,coresight-jtagmm-cpu = <&CPU3>;

		qcom,si-enable;

	};



	rpm_bus: qcom,rpm-smd {

		 compatible = "qcom,rpm-glink";

		 qcom,glink-edge = "rpm";