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Commit 04a4c1d9 authored by Sarangdhar Joshi's avatar Sarangdhar Joshi
Browse files

ARM: dts: msm: separate jtagv8-mm device tree changes for msm8996 



Some of the workarounds for saving and restoring of ETM registers
are not applicable for MSM8996 V3. Separate version specific
device tree changes for ETM registers.

Change-Id: I125cc107dc443b49d52e76af030faf6aa4201432
Signed-off-by: default avatarSarangdhar Joshi <spjoshi@codeaurora.org>
parent 6b6b4c37

arch/arm/boot/dts/qcom/msm8996-v2.dtsi

+52 −0
Original line number Diff line number Diff line
@@ -585,6 +585,58 @@ 
			qcom,levels = <4 5 5>; /* Nominal, Turbo, Turbo */

		};

	};



	jtag_mm0: jtagmm@3840000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x3840000 0x1000>;

		reg-names = "etm-base";



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";



		qcom,coresight-jtagmm-cpu = <&CPU0>;

		qcom,si-enable;

	};



	jtag_mm1: jtagmm@3940000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x3940000 0x1000>;

		reg-names = "etm-base";



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";



		qcom,coresight-jtagmm-cpu = <&CPU1>;

		qcom,si-enable;

	};



	jtag_mm2: jtagmm@3a40000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x3a40000 0x1000>;

		reg-names = "etm-base";



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";



		qcom,coresight-jtagmm-cpu = <&CPU2>;

		qcom,si-enable;

	};



	jtag_mm3: jtagmm@3b40000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x3b40000 0x1000>;

		reg-names = "etm-base";



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";



		qcom,coresight-jtagmm-cpu = <&CPU3>;

		qcom,si-enable;

	};

};



&tsens0 {

arch/arm/boot/dts/qcom/msm8996-v3.dtsi

+50 −0
Original line number Diff line number Diff line
@@ -158,6 +158,56 @@ 
	};

};



&soc {

	jtag_mm0: jtagmm@3840000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x3840000 0x1000>;

		reg-names = "etm-base";



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";



		qcom,coresight-jtagmm-cpu = <&CPU0>;

	};



	jtag_mm1: jtagmm@3940000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x3940000 0x1000>;

		reg-names = "etm-base";



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";



		qcom,coresight-jtagmm-cpu = <&CPU1>;

	};



	jtag_mm2: jtagmm@3a40000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x3a40000 0x1000>;

		reg-names = "etm-base";



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";



		qcom,coresight-jtagmm-cpu = <&CPU2>;

	};



	jtag_mm3: jtagmm@3b40000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x3b40000 0x1000>;

		reg-names = "etm-base";



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";



		qcom,coresight-jtagmm-cpu = <&CPU3>;

	};

};



&mdss_hdmi_pll {

	compatible = "qcom,mdss_hdmi_pll_8996_v3";

};

arch/arm/boot/dts/qcom/msm8996.dtsi

+0 −52
Original line number Diff line number Diff line
@@ -1993,58 +1993,6 @@ 
		reg-names = "fuse-base";

	};



	jtag_mm0: jtagmm@3840000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x3840000 0x1000>;

		reg-names = "etm-base";



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";



		qcom,coresight-jtagmm-cpu = <&CPU0>;

		qcom,si-enable;

	};



	jtag_mm1: jtagmm@3940000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x3940000 0x1000>;

		reg-names = "etm-base";



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";



		qcom,coresight-jtagmm-cpu = <&CPU1>;

		qcom,si-enable;

	};



	jtag_mm2: jtagmm@3a40000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x3a40000 0x1000>;

		reg-names = "etm-base";



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";



		qcom,coresight-jtagmm-cpu = <&CPU2>;

		qcom,si-enable;

	};



	jtag_mm3: jtagmm@3b40000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x3b40000 0x1000>;

		reg-names = "etm-base";



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";



		qcom,coresight-jtagmm-cpu = <&CPU3>;

		qcom,si-enable;

	};



	rpm_bus: qcom,rpm-smd {

		 compatible = "qcom,rpm-glink";

		 qcom,glink-edge = "rpm";