clk: msm: clock-alpha-pll: Support hardware FSM mode

Some PLL implementations support HW control of PLLs,
and it is expected that software does not enable
or disable the PLLs explicitly. Everything else
with respect to PLL configuration remains the same.

Note that this is different from the FSM mode where
software enables/disables the PLL using a vote
register.

Change-Id: Id44bcdd756bccd9ed490629a76eadc664029639a
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>