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Commit 87d13f7a authored by David Collins's avatar David Collins
Browse files

ARM: dts: msm: add a VDD_APCC CPR3 regulator subnode for CBF clk on msm8996 



Add a cpr3-regulator device subnode which defines a new regulator
interface for thread 0 of the VDD_APCC CPR supply.  Update the
CBF clock device to use this new regulator and its independent
voltage corners.  Adjust the CBF clock frequency to voltage
corner mapping table to use CBF regulator corner values instead
of power cluster regulator corner values.

By switching the CBF clock to use a separate regulator, the power
cluster is able to utilize LDO mode when the power cluster is
operating at a lower frequency than the performance cluster.

Also relax the thread 0 power cluster floor voltages so that they
correspond exactly to the requirements of the power cluster
instead of the max of the power cluster and CBF clock
requirements.

Change-Id: Iee6f3d8c22de83b56796934d207d462318213558
Signed-off-by: default avatarDavid Collins <collinsd@codeaurora.org>
parent c0aaceac

arch/arm/boot/dts/qcom/msm8996-regulator.dtsi

+51 −4
Original line number Diff line number Diff line
@@ -586,8 +586,8 @@ 
			qcom,cpr-up-threshold = <0>;

			qcom,cpr-down-threshold = <2>;



			apc0_vreg: regulator {

				regulator-name = "apc0_corner";

			apc0_pwrcl_vreg: regulator-pwrcl {

				regulator-name = "apc0_pwrcl_corner";

				regulator-min-microvolt = <1>;

				regulator-max-microvolt = <19>;
@@ -608,8 +608,8 @@ 
					1015000 1015000 1015000 1015000>;

				qcom,cpr-voltage-floor =

					<520000  550000  555000  565000  585000

					 635000  635000  660000  690000  730000

					 750000  750000  760000  770000  780000

					 615000  635000  655000  690000  720000

					 740000  750000  760000  770000  780000

					 790000  815000  840000  850000>;

				qcom,corner-frequencies =

					<192000000  268800000  307200000
@@ -641,6 +641,53 @@ 
				qcom,allow-quotient-interpolation;

				qcom,cpr-scaled-open-loop-voltage-as-ceiling;

			};



			apc0_cbf_vreg: regulator-cbf {

				regulator-name = "apc0_cbf_corner";

				regulator-min-microvolt = <1>;

				regulator-max-microvolt = <10>;



				qcom,cpr-pd-bypass-mask = <0x18>;

				qcom,cpr-fuse-corners = <5>;

				qcom,cpr-fuse-combos = <1>;

				qcom,cpr-corners = <10>;



				qcom,cpr-corner-fmax-map = <1 2 5 9 10>;



				qcom,cpr-voltage-ceiling =

				       <605000  670000  745000  745000  745000

					905000  905000  905000  905000 1015000>;

				qcom,cpr-voltage-floor =

				       <520000  545000  565000  595000  635000

					660000  690000  730000  750000  850000>;



				qcom,corner-frequencies =

					<150000000  307200000  384000000

					 499200000  595200000  691200000

					 787200000  883200000  960000000

					1036800000>;



				qcom,cpr-ro-scaling-factor =

				      <   0    0    0    0 2222 2275 2506 2491

				       2649 2640 2886 2866    0    0    0    0>,

				      <   0    0    0    0 2222 2275 2506 2491

				       2649 2640 2886 2866    0    0    0    0>,

				      <   0    0    0    0 2222 2275 2506 2491

				       2649 2640 2886 2866    0    0    0    0>,

				      <   0    0    0    0 2147 2226 2310 2312

				       2450 2447 2603 2600    0    0    0    0>,

				      <   0    0    0    0 1989 2079 2066 2083

				       2193 2201 2283 2296    0    0    0    0>;



				qcom,cpr-open-loop-voltage-fuse-adjustment =

					<0 0 0 0 0>;

				qcom,cpr-closed-loop-voltage-fuse-adjustment =

					<0 0 0 0 0>;



				qcom,allow-voltage-interpolation;

				qcom,allow-quotient-interpolation;

				qcom,cpr-scaled-open-loop-voltage-as-ceiling;

			};

		};



		thread@1 {

arch/arm/boot/dts/qcom/msm8996-v2.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -25,7 +25,7 @@ 
	qcom,msm-id = <246 0x20001>;

};



&apc0_vreg {

&apc0_pwrcl_vreg {

	qcom,ldo-disable;

};

arch/arm/boot/dts/qcom/msm8996.dtsi

+10 −10
Original line number Diff line number Diff line
@@ -739,9 +739,9 @@ 
		      <0x00070130    0x8>,

		      <0x09820000 0x1000>;

		reg-names = "pwrcl_pll", "perfcl_pll", "cbf_pll", "pwrcl_mux", "perfcl_mux", "cbf_mux", "efuse", "debug";

		vdd-pwrcl-supply = <&apc0_vreg>;

		vdd-pwrcl-supply = <&apc0_pwrcl_vreg>;

		vdd-perfcl-supply = <&apc1_vreg>;

		vdd-cbf-supply = <&apc0_vreg>;

		vdd-cbf-supply = <&apc0_cbf_vreg>;

		vdd-dig-supply = <&pm8994_s2_corner_ao>;

		cbf-dev = <&m4m_cache>;

		qcom,pwrcl-speedbin0-v0 =
@@ -786,14 +786,14 @@ 
		qcom,cbf-speedbin0-v0 =

			<	   0  0 >,

			<  307200000  2 >,

			<  384000000  4 >,

			<  499200000  6 >,

			<  595200000  6 >,

			<  691200000  8 >,

			<  787200000  9 >,

			<  883200000 10 >,

			<  960000000 11 >,

			< 1036800000 19 >;

			<  384000000  3 >,

			<  499200000  4 >,

			<  595200000  5 >,

			<  691200000  6 >,

			<  787200000  7 >,

			<  883200000  8 >,

			<  960000000  9 >,

			< 1036800000 10 >;

		clock-names = "xo_ao", "aux_clk";

		clocks = <&clock_gcc clk_cxo_clk_src_ao>,

			 <&clock_gcc clk_gpll0_ao>;