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Commit 856ac3c6 authored by Yong Zhang's avatar Yong Zhang Committed by Ralf Baechle
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MIPS: BMIPS: delay irq enable to ->smp_finish() 



To prepare for smoothing set_cpu_[active|online]() mess up

Signed-off-by: default avatarYong Zhang <yong.zhang0@gmail.com>
Cc: Sergei Shtylyov <sshtylyov@mvista.com>
Cc: David Daney <david.daney@cavium.com>
Acked-by: default avatarDavid Daney <david.daney@cavium.com>
Patchwork: https://patchwork.linux-mips.org/patch/3846/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 1bcfecc0

arch/mips/kernel/smp-bmips.c

+7 −7
Original line number Diff line number Diff line
@@ -196,13 +196,6 @@ static void bmips_init_secondary(void) 


	write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0));

#endif



	/* make sure there won't be a timer interrupt for a little while */

	write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);



	irq_enable_hazard();

	set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ1 | IE_IRQ5 | ST0_IE);

	irq_enable_hazard();

}



/*
@@ -211,6 +204,13 @@ static void bmips_init_secondary(void) 
static void bmips_smp_finish(void)

{

	pr_info("SMP: CPU%d is running\n", smp_processor_id());



	/* make sure there won't be a timer interrupt for a little while */

	write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);



	irq_enable_hazard();

	set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ1 | IE_IRQ5 | ST0_IE);

	irq_enable_hazard();

}



/*