Merge "soc: qcom: add l2 cache perf events driver"

L2 cache performance monitor unit

L2 cache controllers have a performance monitor unit to measure

events such as cache hits and misses. There is one L2 cache PMU

for each cluster of CPUs.

Required properties:

- compatible : should be "qcom,qcom-l2cache-pmu"

- interrupts : 1 interrupt for each cluster.

- qcom,cpu-affinity: specifies the id of the first CPU in the cluster.

Example:

	l2cache-pmu {

		    compatible = "qcom,qcom-l2cache-pmu";

		    interrupts = <0 0 1>, <0 8 1>;

		    qcom,cpu-affinity = <0>, <2>

	};

	"arm,arm11mpcore-pmu"

	"arm,arm1176-pmu"

	"arm,arm1136-pmu"

	"qcom,kryo-pmuv3"

	"qcom,krait-pmu"

- interrupts : 1 combined interrupt or 1 per core. If the interrupt is a per-cpu

               interrupt (PPI) then 1 interrupt should be specified.

	qcom,slope = <2901 2846 3200 3200 3200 3200 3200 3200 3200

						3200 3200 3200 3200>;

};

/* cpu pmu override */

&cpu_pmu {

	compatible = "qcom,kryo-pmuv3";

};

		};

	};

	cpu-pmu {

	cpu_pmu: cpu-pmu {

		compatible = "arm,armv8-pmuv3";

		qcom,irq-is-percpu;

		interrupts = <1 7 4>;

	struct pmu_hw_events	*(*get_hw_events)(void);

	void			(*save_pm_registers)(void *hcpu);

	void			(*restore_pm_registers)(void *hcpu);

	int			(*check_event)(

					 struct arm_pmu *armpmu,

					 struct hw_perf_event *hwc);

};

#define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))