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Commit 7b4e8333 authored by Deepak Katragadda's avatar Deepak Katragadda
Browse files

clk: msm: clock-gcc-8996: Set core mem bit for gcc_mmss_bimc_gfx_clk 



Set the FORCE_MEM_CORE_ON bit for the gcc_mmss_bimc_gfx_clk once
during clock probe on msm8996 and not toggle it for every
gdsc_gpu power cycle. This should take care of any potential
race conditions between HLOS and other entities leading to memory
corruption.

Change-Id: I10cedd16719280beabc24972e625ad8757b5e1fc
Signed-off-by: default avatarDeepak Katragadda <dkatraga@codeaurora.org>
parent 0600f6c1

arch/arm/boot/dts/qcom/msm8996-v2.dtsi

+2 −3
Original line number Diff line number Diff line
@@ -56,9 +56,8 @@ 
};



&gdsc_gpu_gx {

	clock-names = "bimc_core_clk", "core_clk", "core_root_clk";

	clocks = <&clock_gcc clk_gcc_mmss_bimc_gfx_clk>,

		 <&clock_gpu clk_gpu_gx_gfx3d_clk>,

	clock-names = "core_clk", "core_root_clk";

	clocks = <&clock_gpu clk_gpu_gx_gfx3d_clk>,

		 <&clock_gpu clk_gfx3d_clk_src_v2>;

};

arch/arm/boot/dts/qcom/msm8996-v3.dtsi

+2 −3
Original line number Diff line number Diff line
@@ -60,9 +60,8 @@ 
};



&gdsc_gpu_gx {

	clock-names = "bimc_core_clk", "core_clk", "core_root_clk";

	clocks = <&clock_gcc clk_gcc_mmss_bimc_gfx_clk>,

		 <&clock_gpu clk_gpu_gx_gfx3d_clk>,

	clock-names = "core_clk", "core_root_clk";

	clocks = <&clock_gpu clk_gpu_gx_gfx3d_clk>,

		 <&clock_gpu clk_gfx3d_clk_src_v2>;

};

arch/arm/boot/dts/qcom/msm8996.dtsi

+2 −3
Original line number Diff line number Diff line
@@ -3566,9 +3566,8 @@ 
};



&gdsc_gpu_gx {

	clock-names = "bimc_core_clk", "core_clk", "core_root_clk";

	clocks = <&clock_gcc clk_gcc_mmss_bimc_gfx_clk>,

		 <&clock_gpu clk_gpu_gx_gfx3d_clk>,

	clock-names = "core_clk", "core_root_clk";

	clocks = <&clock_gpu clk_gpu_gx_gfx3d_clk>,

		 <&clock_gpu clk_gfx3d_clk_src>;

	qcom,force-enable-root-clk;

	parent-supply = <&gfx_vreg>;

drivers/clk/msm/clock-gcc-8996.c

+6 −0
Original line number Diff line number Diff line
@@ -3712,6 +3712,12 @@ static int msm_gcc_8996_probe(struct platform_device *pdev) 
	/* Keep an active vote on CXO in case no other driver votes for it */

	clk_prepare_enable(&cxo_clk_src_ao.c);



	/*

	 * Keep the core memory settings enabled at all times for

	 * gcc_mmss_bimc_gfx_clk.

	 */

	clk_set_flags(&gcc_mmss_bimc_gfx_clk.c, CLKFLAG_RETAIN_MEM);



	dev_info(&pdev->dev, "Registered GCC clocks.\n");

	return 0;

}