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Commit 77c32bbb authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'for-linus' of git://git.infradead.org/users/vkoul/slave-dma 

Pull slave-dmaengine updates from Vinod Koul:
 - new Xilixn VDMA driver from Srikanth
 - bunch of updates for edma driver by Thomas, Joel and Peter
 - fixes and updates on dw, ste_dma, freescale, mpc512x, sudmac etc

* 'for-linus' of git://git.infradead.org/users/vkoul/slave-dma: (45 commits)
  dmaengine: sh: don't use dynamic static allocation
  dmaengine: sh: fix print specifier warnings
  dmaengine: sh: make shdma_prep_dma_cyclic static
  dmaengine: Kconfig: Update MXS_DMA help text to include MX6Q/MX6DL
  of: dma: Grammar s/requests/request/, s/used required/required/
  dmaengine: shdma: Enable driver compilation with COMPILE_TEST
  dmaengine: rcar-hpbdma: Include linux/err.h
  dmaengine: sudmac: Include linux/err.h
  dmaengine: sudmac: Keep #include sorted alphabetically
  dmaengine: shdmac: Include linux/err.h
  dmaengine: shdmac: Keep #include sorted alphabetically
  dmaengine: s3c24xx-dma: Add cyclic transfer support
  dmaengine: s3c24xx-dma: Process whole SG chain
  dmaengine: imx: correct sdmac->status for cyclic dma tx
  dmaengine: pch: fix compilation for alpha target
  dmaengine: dw: check return code of dma_async_device_register()
  dmaengine: dw: fix regression in dw_probe() function
  dmaengine: dw: enable clock before access
  dma: pch_dma: Fix Kconfig dependencies
  dmaengine: mpc512x: add support for peripheral transfers
  ...
parents fad0701e 06822788

Documentation/devicetree/bindings/dma/mmp-dma.txt

+7 −4
Original line number Diff line number Diff line 
* MARVELL MMP DMA controller



Marvell Peripheral DMA Controller

Used platfroms: pxa688, pxa910, pxa3xx, etc

Used platforms: pxa688, pxa910, pxa3xx, etc



Required properties:

- compatible: Should be "marvell,pdma-1.0"

- reg: Should contain DMA registers location and length.

- interrupts: Either contain all of the per-channel DMA interrupts

		or one irq for pdma device

- #dma-channels: Number of DMA channels supported by the controller.



Optional properties:

- #dma-channels: Number of DMA channels supported by the controller (defaults

  to 32 when not specified)



"marvell,pdma-1.0"

Used platfroms: pxa25x, pxa27x, pxa3xx, pxa93x, pxa168, pxa910, pxa688.

Used platforms: pxa25x, pxa27x, pxa3xx, pxa93x, pxa168, pxa910, pxa688.



Examples:
@@ -45,7 +48,7 @@ pdma: dma-controller@d4000000 { 




Marvell Two Channel DMA Controller used specifically for audio

Used platfroms: pxa688, pxa910

Used platforms: pxa688, pxa910



Required properties:

- compatible: Should be "marvell,adma-1.0" or "marvell,pxa910-squ"

Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt

0 → 100644
+75 −0
Original line number Diff line number Diff line 
Xilinx AXI VDMA engine, it does transfers between memory and video devices.

It can be configured to have one channel or two channels. If configured

as two channels, one is to transmit to the video device and another is

to receive from the video device.



Required properties:

- compatible: Should be "xlnx,axi-vdma-1.00.a"

- #dma-cells: Should be <1>, see "dmas" property below

- reg: Should contain VDMA registers location and length.

- xlnx,num-fstores: Should be the number of framebuffers as configured in h/w.

- dma-channel child node: Should have at least one channel and can have up to

	two channels per device. This node specifies the properties of each

	DMA channel (see child node properties below).



Optional properties:

- xlnx,include-sg: Tells configured for Scatter-mode in

	the hardware.

- xlnx,flush-fsync: Tells which channel to Flush on Frame sync.

	It takes following values:

	{1}, flush both channels

	{2}, flush mm2s channel

	{3}, flush s2mm channel



Required child node properties:

- compatible: It should be either "xlnx,axi-vdma-mm2s-channel" or

	"xlnx,axi-vdma-s2mm-channel".

- interrupts: Should contain per channel VDMA interrupts.

- xlnx,data-width: Should contain the stream data width, take values

	{32,64...1024}.



Optional child node properties:

- xlnx,include-dre: Tells hardware is configured for Data

	Realignment Engine.

- xlnx,genlock-mode: Tells Genlock synchronization is

	enabled/disabled in hardware.



Example:

++++++++



axi_vdma_0: axivdma@40030000 {

	compatible = "xlnx,axi-vdma-1.00.a";

	#dma_cells = <1>;

	reg = < 0x40030000 0x10000 >;

	xlnx,num-fstores = <0x8>;

	xlnx,flush-fsync = <0x1>;

	dma-channel@40030000 {

		compatible = "xlnx,axi-vdma-mm2s-channel";

		interrupts = < 0 54 4 >;

		xlnx,datawidth = <0x40>;

	} ;

	dma-channel@40030030 {

		compatible = "xlnx,axi-vdma-s2mm-channel";

		interrupts = < 0 53 4 >;

		xlnx,datawidth = <0x40>;

	} ;

} ;





* DMA client



Required properties:

- dmas: a list of <[Video DMA device phandle] [Channel ID]> pairs,

	where Channel ID is '0' for write/tx and '1' for read/rx

	channel.

- dma-names: a list of DMA channel names, one per "dmas" entry



Example:

++++++++



vdmatest_0: vdmatest@0 {

	compatible ="xlnx,axi-vdma-test-1.00.a";

	dmas = <&axi_vdma_0 0

		&axi_vdma_0 1>;

	dma-names = "vdma0", "vdma1";

} ;

arch/powerpc/boot/dts/mpc8308_p1m.dts

+1 −1
Original line number Diff line number Diff line
@@ -296,7 +296,7 @@ 
		};



		dma@2c000 {

			compatible = "fsl,mpc8308-dma", "fsl,mpc5121-dma";

			compatible = "fsl,mpc8308-dma";

			reg = <0x2c000 0x1800>;

			interrupts = <3 0x8

					94 0x8>;

arch/powerpc/boot/dts/mpc8308rdb.dts

+1 −1
Original line number Diff line number Diff line
@@ -265,7 +265,7 @@ 
		};



		dma@2c000 {

			compatible = "fsl,mpc8308-dma", "fsl,mpc5121-dma";

			compatible = "fsl,mpc8308-dma";

			reg = <0x2c000 0x1800>;

			interrupts = <3 0x8

					94 0x8>;

drivers/dma/Kconfig

+16 −2
Original line number Diff line number Diff line
@@ -234,7 +234,7 @@ config PL330_DMA 


config PCH_DMA

	tristate "Intel EG20T PCH / LAPIS Semicon IOH(ML7213/ML7223/ML7831) DMA"

	depends on PCI && X86

	depends on PCI && (X86_32 || COMPILE_TEST)

	select DMA_ENGINE

	help

	  Enable support for Intel EG20T PCH DMA engine.
@@ -269,7 +269,7 @@ config MXS_DMA 
	select DMA_ENGINE

	help

	  Support the MXS DMA engine. This engine including APBH-DMA

	  and APBX-DMA is integrated into Freescale i.MX23/28 chips.

	  and APBX-DMA is integrated into Freescale i.MX23/28/MX6Q/MX6DL chips.



config EP93XX_DMA

	bool "Cirrus Logic EP93xx DMA support"
@@ -361,6 +361,20 @@ config FSL_EDMA 
	  multiplexing capability for DMA request sources(slot).

	  This module can be found on Freescale Vybrid and LS-1 SoCs.



config XILINX_VDMA

	tristate "Xilinx AXI VDMA Engine"

	depends on (ARCH_ZYNQ || MICROBLAZE)

	select DMA_ENGINE

	help

	  Enable support for Xilinx AXI VDMA Soft IP.



	  This engine provides high-bandwidth direct memory access

	  between memory and AXI4-Stream video type target

	  peripherals including peripherals which support AXI4-

	  Stream Video Protocol.  It has two stream interfaces/

	  channels, Memory Mapped to Stream (MM2S) and Stream to

	  Memory Mapped (S2MM) for the data transfers.



config DMA_ENGINE

	bool