Loading arch/arm/boot/dts/qcom/msm8996-v2.dtsi +2 −3 Original line number Diff line number Diff line Loading @@ -56,9 +56,8 @@ }; &gdsc_gpu_gx { clock-names = "bimc_core_clk", "core_clk", "core_root_clk"; clocks = <&clock_gcc clk_gcc_mmss_bimc_gfx_clk>, <&clock_gpu clk_gpu_gx_gfx3d_clk>, clock-names = "core_clk", "core_root_clk"; clocks = <&clock_gpu clk_gpu_gx_gfx3d_clk>, <&clock_gpu clk_gfx3d_clk_src_v2>; }; Loading arch/arm/boot/dts/qcom/msm8996-v3.dtsi +2 −3 Original line number Diff line number Diff line Loading @@ -60,9 +60,8 @@ }; &gdsc_gpu_gx { clock-names = "bimc_core_clk", "core_clk", "core_root_clk"; clocks = <&clock_gcc clk_gcc_mmss_bimc_gfx_clk>, <&clock_gpu clk_gpu_gx_gfx3d_clk>, clock-names = "core_clk", "core_root_clk"; clocks = <&clock_gpu clk_gpu_gx_gfx3d_clk>, <&clock_gpu clk_gfx3d_clk_src_v2>; }; Loading arch/arm/boot/dts/qcom/msm8996.dtsi +2 −3 Original line number Diff line number Diff line Loading @@ -3558,9 +3558,8 @@ }; &gdsc_gpu_gx { clock-names = "bimc_core_clk", "core_clk", "core_root_clk"; clocks = <&clock_gcc clk_gcc_mmss_bimc_gfx_clk>, <&clock_gpu clk_gpu_gx_gfx3d_clk>, clock-names = "core_clk", "core_root_clk"; clocks = <&clock_gpu clk_gpu_gx_gfx3d_clk>, <&clock_gpu clk_gfx3d_clk_src>; qcom,force-enable-root-clk; parent-supply = <&gfx_vreg>; Loading drivers/clk/msm/clock-gcc-8996.c +6 −0 Original line number Diff line number Diff line Loading @@ -3714,6 +3714,12 @@ static int msm_gcc_8996_probe(struct platform_device *pdev) /* Keep an active vote on CXO in case no other driver votes for it */ clk_prepare_enable(&cxo_clk_src_ao.c); /* * Keep the core memory settings enabled at all times for * gcc_mmss_bimc_gfx_clk. */ clk_set_flags(&gcc_mmss_bimc_gfx_clk.c, CLKFLAG_RETAIN_MEM); dev_info(&pdev->dev, "Registered GCC clocks.\n"); return 0; } Loading Loading
arch/arm/boot/dts/qcom/msm8996-v2.dtsi +2 −3 Original line number Diff line number Diff line Loading @@ -56,9 +56,8 @@ }; &gdsc_gpu_gx { clock-names = "bimc_core_clk", "core_clk", "core_root_clk"; clocks = <&clock_gcc clk_gcc_mmss_bimc_gfx_clk>, <&clock_gpu clk_gpu_gx_gfx3d_clk>, clock-names = "core_clk", "core_root_clk"; clocks = <&clock_gpu clk_gpu_gx_gfx3d_clk>, <&clock_gpu clk_gfx3d_clk_src_v2>; }; Loading
arch/arm/boot/dts/qcom/msm8996-v3.dtsi +2 −3 Original line number Diff line number Diff line Loading @@ -60,9 +60,8 @@ }; &gdsc_gpu_gx { clock-names = "bimc_core_clk", "core_clk", "core_root_clk"; clocks = <&clock_gcc clk_gcc_mmss_bimc_gfx_clk>, <&clock_gpu clk_gpu_gx_gfx3d_clk>, clock-names = "core_clk", "core_root_clk"; clocks = <&clock_gpu clk_gpu_gx_gfx3d_clk>, <&clock_gpu clk_gfx3d_clk_src_v2>; }; Loading
arch/arm/boot/dts/qcom/msm8996.dtsi +2 −3 Original line number Diff line number Diff line Loading @@ -3558,9 +3558,8 @@ }; &gdsc_gpu_gx { clock-names = "bimc_core_clk", "core_clk", "core_root_clk"; clocks = <&clock_gcc clk_gcc_mmss_bimc_gfx_clk>, <&clock_gpu clk_gpu_gx_gfx3d_clk>, clock-names = "core_clk", "core_root_clk"; clocks = <&clock_gpu clk_gpu_gx_gfx3d_clk>, <&clock_gpu clk_gfx3d_clk_src>; qcom,force-enable-root-clk; parent-supply = <&gfx_vreg>; Loading
drivers/clk/msm/clock-gcc-8996.c +6 −0 Original line number Diff line number Diff line Loading @@ -3714,6 +3714,12 @@ static int msm_gcc_8996_probe(struct platform_device *pdev) /* Keep an active vote on CXO in case no other driver votes for it */ clk_prepare_enable(&cxo_clk_src_ao.c); /* * Keep the core memory settings enabled at all times for * gcc_mmss_bimc_gfx_clk. */ clk_set_flags(&gcc_mmss_bimc_gfx_clk.c, CLKFLAG_RETAIN_MEM); dev_info(&pdev->dev, "Registered GCC clocks.\n"); return 0; } Loading