Merge "ARM: dts: msm: add tlmm_mem resouce to sdhc_1 for mdmfermium" (73f6db18) · Commits · e / devices / android_kernel_xiaomi_markw

Documentation/devicetree/bindings/mmc/sdhci-msm.txt

+1 −0

Original line number	Diff line number	Diff line
		@@ -7,6 +7,7 @@ Required properties:
		- reg : should contain SDHC, SD Core register map.
		- reg-names : indicates various resources passed to driver (via reg proptery) by name.
		Required "reg-names" are "hc_mem" and "core_mem"
		optional ones are "tlmm_mem"
		- interrupts : should contain SDHC interrupts.
		- interrupt-names : indicates interrupts passed to driver (via interrupts property) by name.
		Required "interrupt-names" are "hc_irq" and "pwr_irq".

arch/arm/boot/dts/qcom/mdmfermium-cdp.dtsi

+19 −0

Original line number	Diff line number	Diff line
		@@ -88,3 +88,22 @@
		qcom,irq-gpio = <&pm8019_mpps 2 0>;
		};
		};

		&sdhc_1 {
		vdd-io-supply = <&mdmfermium_l11>;
		qcom,vdd-io-always-on;
		qcom,vdd-io-voltage-level = <1800000 1800000>;
		qcom,vdd-io-current-level = <0 30000>;

		pinctrl-names = "active", "sleep";
		pinctrl-0 = <&pmx_sdc1_clk_on &pmx_sdc1_cmd_on &pmx_sdc1_data_on
		&sdc1_wlan_gpio_active>;
		pinctrl-1 = <&pmx_sdc1_clk_off &pmx_sdc1_cmd_off &pmx_sdc1_data_off>;
		qcom,nonremovable;
		qcom,core_3_0v_support;
		status = "ok";
		};

		&usb_otg {
		vbus_otg-supply = <&smb358_otg_vreg>;
		};

arch/arm/boot/dts/qcom/mdmfermium-mtp.dtsi

+15 −0

Original line number	Diff line number	Diff line
		@@ -76,6 +76,21 @@
		};
		};

		&sdhc_1 {
		vdd-io-supply = <&mdmfermium_l11>;
		qcom,vdd-io-always-on;
		qcom,vdd-io-voltage-level = <1800000 1800000>;
		qcom,vdd-io-current-level = <0 30000>;

		pinctrl-names = "active", "sleep";
		pinctrl-0 = <&pmx_sdc1_clk_on &pmx_sdc1_cmd_on &pmx_sdc1_data_on
		&sdc1_wlan_gpio_active>;
		pinctrl-1 = <&pmx_sdc1_clk_off &pmx_sdc1_cmd_off &pmx_sdc1_data_off>;
		qcom,nonremovable;
		qcom,core_3_0v_support;
		status = "ok";
		};

		&i2c_4 {
		/* SMB358 charger configuration */
		smb358_otg_vreg: smb358-charger@57 {

arch/arm/boot/dts/qcom/mdmfermium-pinctrl.dtsi

+70 −0

Original line number	Diff line number	Diff line
		@@ -122,6 +122,76 @@
		};
		};

		/* SDC pin type */

		pmx_sdc1_cmd {
		pmx_sdc1_cmd_on: pmx_sdc1_cmd_on {
		config {
		pins = "sdc1_cmd";
		drive-strength = <10>;
		bias-pull-up;
		};
		};

		pmx_sdc1_cmd_off: pmx_sdc1_cmd_off {
		config {
		pins = "sdc1_cmd";
		bias-pull-up;
		drive-strength = <2>;
		};
		};
		};

		pmx_sdc1_clk {
		pmx_sdc1_clk_on: pmx_sdc1_clk_on {
		config {
		pins = "sdc1_clk";
		drive-strength = <16>;
		bias-disable;
		};
		};

		pmx_sdc1_clk_off: pmx_sdc1_clk_off {
		config {
		pins = "sdc1_clk";
		drive-strength = <2>;
		bias-disable;
		};
		};
		};

		pmx_sdc1_data {
		pmx_sdc1_data_on: pmx_sdc1_data_on {
		config {
		pins = "sdc1_data";
		bias-pull-up;
		drive-strength = <10>;
		};
		};

		pmx_sdc1_data_off: pmx_sdc1_data_off {
		config {
		pins = "sdc1_data";
		bias-pull-up;
		drive-strength = <2>;
		};
		};
		};

		sdc1_wlan_gpio {
		sdc1_wlan_gpio_active: sdc1_wlan_gpio_active {
		mux {
		pins = "gpio38";
		function = "gpio";
		};
		config {
		pins = "gpio38";
		output-high;
		drive-strength = <8>;
		bias-pull-up;
		};
		};
		};

		i2c_4 {
		i2c_4_active: i2c_4_active {

arch/arm/boot/dts/qcom/mdmfermium.dtsi

+53 −1

Original line number	Diff line number	Diff line
		@@ -24,6 +24,7 @@
		interrupt-parent = <&intc>;

		aliases {
		sdhc1 = &sdhc_1;/* SDC1 for SDIO slot */
		qpic_nand1 = &qnand_1;
		};

		@@ -605,6 +606,57 @@
		status = "disabled";
		};

		sdhc_1: sdhci@7824900 {
		compatible = "qcom,sdhci-msm";
		reg = <0x7824900 0x200>, <0x7824000 0x800>, <0x01111000 0x4>;
		reg-names = "hc_mem", "core_mem", "tlmm_mem";

		qcom,cpu-dma-latency-us = <701>;
		qcom,bus-width = <4>;
		gpios = <&tlmm_pinmux 16 0>, /* CLK */
		<&tlmm_pinmux 17 0>, /* CMD */
		<&tlmm_pinmux 15 0>, /* DATA0 */
		<&tlmm_pinmux 14 0>, /* DATA1 */
		<&tlmm_pinmux 13 0>, /* DATA2 */
		<&tlmm_pinmux 12 0>; /* DATA3 */
		qcom,gpio-names = "CLK", "CMD", "DAT0", "DAT1", "DAT2", "DAT3";

		qcom,clk-rates = <400000 20000000 25000000 50000000 100000000
		200000000>;

		clock-names = "iface_clk", "core_clk";
		clocks = <&clock_gcc clk_gcc_sdcc1_ahb_clk>,
		<&clock_gcc clk_gcc_sdcc1_apps_clk>;

		qcom,msm-bus,name = "sdhc1";
		qcom,msm-bus,num-cases = <8>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps = <78 512 0 0>, /* No vote */
		<78 512 1600 3200>, /* 400 KB/s*/
		<78 512 80000 160000>, /* 20 MB/s */
		<78 512 100000 200000>, /* 25 MB/s */
		<78 512 200000 400000>, /* 50 MB/s */
		<78 512 400000 800000>, /* 100 MB/s */
		<78 512 800000 800000>, /* 200 MB/s */
		<78 512 2048000 4096000>; /* Max. bandwidth */
		qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000
		50000000 100000000 200000000 4294967295>;

		#address-cells = <0>;
		interrupt-parent = <&sdhc_1>;
		interrupts = <0 1 2>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0xffffffff>;
		interrupt-map = <0 &intc 0 123 0
		1 &intc 0 138 0
		2 &tlmm_pinmux 14 0x8>;
		interrupt-names = "hc_irq", "pwr_irq", "sdiowakeup_irq";

		qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50",
		"DDR50","SDR104";
		status = "disabled";
		};

		tsens: tsens@4a8000 {
		compatible = "qcom,mdmfermium-tsens";
		reg = <0x4a8000 0x2000>,