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Commit 71328762 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add support for clock cpu for MSMtitanium"

parents a912bfc5 d511026a

arch/arm/boot/dts/qcom/msmtitanium-rumi.dts

+4 −0
Original line number Diff line number Diff line
@@ -108,3 +108,7 @@ 
&pmtitanium_adc_tm {

	status = "disabled";

};



&clock_cpu {

	compatible = "qcom,dummycc";

};

arch/arm/boot/dts/qcom/msmtitanium.dtsi

+40 −0
Original line number Diff line number Diff line
@@ -708,6 +708,46 @@ 
		#clock-cells = <1>;

	};



	clock_cpu: qcom,cpu-clock-titanium@b116000 {

		compatible = "qcom,cpu-clock-titanium";

		reg =   <0xb114000  0x68>,

			<0xb014000  0x68>,

			<0xb116000  0x400>,

			<0xb111050  0x08>,

			<0xb011050  0x08>,

			<0xb1d1050  0x08>,

			<0x00a4124  0x08>;

		reg-names = "rcgwr-c0-base", "rcgwr-c1-base",

			    "c0-pll", "c0-mux", "c1-mux",

			    "cci-mux", "efuse";

		vdd-mx-supply = <&pmtitanium_s7_level_ao>;

		vdd-cl-supply = <&apc_vreg>;

		clocks = <&clock_gcc clk_xo_a_clk_src>;

		clock-names = "xo_a";

		qcom,num-clusters = <2>;

		qcom,speed0-bin-v0-cl =

			<          0 0>,

			<  652800000 1>,

			< 1036800000 2>,

			< 1401600000 3>,

			< 1689600000 4>,

			< 1843200000 5>,

			< 1958400000 6>,

			< 2150400000 7>,

			< 2208000000 8>;

		qcom,speed0-bin-v0-cci =

			<          0 0>,

			<  307200000 1>,

			<  414720000 2>,

			<  560640000 3>,

			<  675840000 4>,

			<  737280000 5>,

			<  783360000 6>,

			<  860160000 7>,

			<  883200000 8>;

		#clock-cells = <1>;

	};



	rpm_bus: qcom,rpm-smd {

		compatible = "qcom,rpm-smd";

		rpm-channel-name = "rpm_requests";

drivers/clk/msm/clock-cpu-titanium.c

+3 −0
Original line number Diff line number Diff line
@@ -112,6 +112,8 @@ static struct pll_clk apcs_hf_pll = { 
	.test_ctl_lo_reg = (void __iomem *)APCS_PLL_TEST_CTL_LO,

	.test_ctl_hi_reg = (void __iomem *)APCS_PLL_TEST_CTL_HI,

	.status_reg = (void __iomem *)APCS_PLL_MODE,

	.init_test_ctl = true,

	.test_ctl_dbg = true,

	.masks = {

		.pre_div_mask = BIT(12),

		.post_div_mask = BM(9, 8),
@@ -937,6 +939,7 @@ static int __init cpu_clock_pwr_init(void) 


	__variable_rate_pll_init(&apcs_hf_pll.c);

	apcs_hf_pll.c.ops->set_rate(&apcs_hf_pll.c, pwrcl_early_boot_rate);

	clk_ops_variable_rate_pll.enable(&apcs_hf_pll.c);



	base = ioremap_nocache(APCS_ALIAS1_CMD_RCGR, SZ_8);

	regval = readl_relaxed(base);

drivers/clk/msm/clock-pll.c

+11 −9
Original line number Diff line number Diff line
@@ -338,6 +338,7 @@ static int variable_rate_pll_clk_enable(struct clk *c) 
		writel_relaxed(pll->vals.test_ctl_lo_val,

				PLL_TEST_CTL_LO_REG(pll));



	if (!pll->test_ctl_dbg) {

		/* Enable test_ctl debug */

		mode |= BIT(3);

		writel_relaxed(mode, PLL_MODE_REG(pll));
@@ -348,6 +349,7 @@ static int variable_rate_pll_clk_enable(struct clk *c) 
		writel_relaxed(testlo, PLL_TEST_CTL_LO_REG(pll));

		/* Wait for the write to complete */

		mb();

	}



	/* Disable PLL bypass mode. */

	mode |= PLL_BYPASSNL;

include/soc/qcom/clock-pll.h

+2 −0
Original line number Diff line number Diff line
@@ -128,6 +128,7 @@ static inline struct pll_vote_clk *to_pll_vote_clk(struct clk *c) 
 * @status_reg: status register, contains the lock detection bit

 * @init_test_ctl: initialize the test control register

 * @pgm_test_ctl_enable: program the test_ctl register in the enable sequence

 * @test_ctl_dbg: if false will configure the test control registers.

 * @masks: masks used for settings in config_reg

 * @vals: configuration values to be written to PLL registers

 * @freq_tbl: pll freq table
@@ -151,6 +152,7 @@ struct pll_clk { 


	bool init_test_ctl;

	bool pgm_test_ctl_enable;

	bool test_ctl_dbg;



	struct pll_config_masks masks;

	struct pll_config_vals vals;