Loading arch/arm/boot/dts/qcom/msm8996-coresight-v2.dtsi +2 −0 Original line number Diff line number Diff line Loading @@ -24,6 +24,7 @@ qcom,memory-size = <0x400000>; qcom,tmc-flush-powerdown; qcom,sg-enable; qcom,force-reg-dump; coresight-id = <0>; coresight-name = "coresight-tmc-etr"; Loading Loading @@ -93,6 +94,7 @@ coresight-ctis = <&cti0 &cti8>; qcom,tmc-flush-powerdown; qcom,force-reg-dump; clocks = <&clock_gcc clk_qdss_clk>, <&clock_gcc clk_qdss_a_clk>; Loading arch/arm/boot/dts/qcom/msm8996-coresight-v3.dtsi +2 −0 Original line number Diff line number Diff line Loading @@ -22,6 +22,7 @@ qcom,memory-size = <0x400000>; qcom,tmc-flush-powerdown; qcom,sg-enable; qcom,force-reg-dump; coresight-id = <0>; coresight-name = "coresight-tmc-etr"; Loading Loading @@ -91,6 +92,7 @@ coresight-ctis = <&cti0 &cti8>; qcom,tmc-flush-powerdown; qcom,force-reg-dump; clocks = <&clock_gcc clk_qdss_clk>, <&clock_gcc clk_qdss_a_clk>; Loading Loading
arch/arm/boot/dts/qcom/msm8996-coresight-v2.dtsi +2 −0 Original line number Diff line number Diff line Loading @@ -24,6 +24,7 @@ qcom,memory-size = <0x400000>; qcom,tmc-flush-powerdown; qcom,sg-enable; qcom,force-reg-dump; coresight-id = <0>; coresight-name = "coresight-tmc-etr"; Loading Loading @@ -93,6 +94,7 @@ coresight-ctis = <&cti0 &cti8>; qcom,tmc-flush-powerdown; qcom,force-reg-dump; clocks = <&clock_gcc clk_qdss_clk>, <&clock_gcc clk_qdss_a_clk>; Loading
arch/arm/boot/dts/qcom/msm8996-coresight-v3.dtsi +2 −0 Original line number Diff line number Diff line Loading @@ -22,6 +22,7 @@ qcom,memory-size = <0x400000>; qcom,tmc-flush-powerdown; qcom,sg-enable; qcom,force-reg-dump; coresight-id = <0>; coresight-name = "coresight-tmc-etr"; Loading Loading @@ -91,6 +92,7 @@ coresight-ctis = <&cti0 &cti8>; qcom,tmc-flush-powerdown; qcom,force-reg-dump; clocks = <&clock_gcc clk_qdss_clk>, <&clock_gcc clk_qdss_a_clk>; Loading