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Commit 6fceacac authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "clk: msm: clock-cpu: Add support for hardware boost and vmin"

parents c3b50ce6 7e9c36a7

Documentation/devicetree/bindings/arm/msm/clock-cpu-titanium.txt

+48 −0
Original line number Diff line number Diff line
@@ -35,6 +35,18 @@ Required properties: 
			the right table is picked from multiple possible tables.

			'ZZZ' can be cl for(c0 & c1) or cci depending on whether

			the table for the clusters or cci.



Optional Properties:

- qcom,pboost-delta:    Array of performance boost frequencies (in MHz). If

			defined, the "safe_l" value column is required to be

			defined along with speedX-bin-vY-cl as indicated in

			below example.

- qcom,enable-vmin:     Boolean property if defined denotes presence of VMin

			reduction available for clusters.

			If defined, the "safe_l" value column is required to be

			defined along with speedX-bin-vY-cl as indicated in

			below example.



Example:

	clock_cpu: qcom,cpu-clock-titanium@b116000 {

		compatible = "qcom,cpu-clock-titanium";
@@ -62,3 +74,39 @@ Example: 
		#address-cells = <1>;

		#size-cells = <1>;

	};



In case vmin & boost delta defined.



	clock_cpu: qcom,cpu-clock-titanium@b116000 {

		compatible = "qcom,cpu-clock-titanium";

		reg =   <0xb114000  0x68>,

			<0xb014000  0x68>,

			<0xb116000  0x400>,

			<0xb111050  0x08>,

			<0xb011050  0x08>,

			<0xb1d1050  0x08>,

			<0x00a412c  0x08>;

		reg-names = "rcgwr-c0-base", "rcgwr-c1-base",

			    "c0-pll", "c0-mux", "c1-mux",

			    "cci-mux", "efuse";

		vdd-mx-supply = <&pmtitanium_s7_level_ao>;

		vdd-cl-supply = <&apc_vreg_corner>;

		clocks = <&clock_gcc clk_xo_a_clk_src>;

		clock-names = "xo_a";

		qcom,enable-vmin;

		qcom,num-clusters = <2>;

		qcom,speed0-bin-v0-cl =

			/*            safe_L */

			<          0 0 0>,

			< 652800000  1 (-1)>,

			< 2150400000 6 102 >,

			< 2208000000 7 104 >;

		qcom,speed0-bin-v0-cci =

			<          0 0>,

			<  261120000 1>,

			<  860160000 6>,

			<  883200000 7>;

		qcom,pboost-delta = <0 50 100>;

		#address-cells = <1>;

		#size-cells = <1>;

	};

arch/arm/boot/dts/qcom/msmtitanium.dtsi

+3 −2
Original line number Diff line number Diff line
@@ -839,13 +839,14 @@ 
		compatible = "qcom,cpu-clock-titanium";

		reg =   <0xb114000  0x68>,

			<0xb014000  0x68>,

			<0xb116000  0x400>,

			<0xb116000  0x330>,

			<0xb016000  0x330>,

			<0xb111050  0x08>,

			<0xb011050  0x08>,

			<0xb1d1050  0x08>,

			<0x00a4124  0x08>;

		reg-names = "rcgwr-c0-base", "rcgwr-c1-base",

			    "c0-pll", "c0-mux", "c1-mux",

			    "c0-pll", "c1-pll", "c0-mux", "c1-mux",

			    "cci-mux", "efuse";

		vdd-mx-supply = <&pmtitanium_s7_level_ao>;

		vdd-cl-supply = <&apc_vreg>;

drivers/clk/msm/clock-cpu-titanium.c

+920 −45

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