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Commit 7e9c36a7 authored by Taniya Das's avatar Taniya Das Committed by Gerrit - the friendly Code Review server
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clk: msm: clock-cpu: Add support for hardware boost and vmin 



The performance boost enhances the voltage and over clocks the CPU
subsystem when less number of cores are online. The limit on how many
cores can run at this higher voltage/frequency corner can be dynamically
programmable by software.

The CPR sensors give the recommendation of voltage based on the frequency
at which the cores are running. But it is ignorant of the number of online
cores and gives feedback assuming all the cores are online. But if less
number of cores are online, we can further reduce the voltage to save
power. The vmin reduction FSM does that precisely.

Change-Id: I305c916f0f7a5fc8deec07caee7e290344d70825
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent ea43e201

Documentation/devicetree/bindings/arm/msm/clock-cpu-titanium.txt

+48 −0
Original line number Diff line number Diff line
@@ -35,6 +35,18 @@ Required properties: 
			the right table is picked from multiple possible tables.

			'ZZZ' can be cl for(c0 & c1) or cci depending on whether

			the table for the clusters or cci.



Optional Properties:

- qcom,pboost-delta:    Array of performance boost frequencies (in MHz). If

			defined, the "safe_l" value column is required to be

			defined along with speedX-bin-vY-cl as indicated in

			below example.

- qcom,enable-vmin:     Boolean property if defined denotes presence of VMin

			reduction available for clusters.

			If defined, the "safe_l" value column is required to be

			defined along with speedX-bin-vY-cl as indicated in

			below example.



Example:

	clock_cpu: qcom,cpu-clock-titanium@b116000 {

		compatible = "qcom,cpu-clock-titanium";
@@ -62,3 +74,39 @@ Example: 
		#address-cells = <1>;

		#size-cells = <1>;

	};



In case vmin & boost delta defined.



	clock_cpu: qcom,cpu-clock-titanium@b116000 {

		compatible = "qcom,cpu-clock-titanium";

		reg =   <0xb114000  0x68>,

			<0xb014000  0x68>,

			<0xb116000  0x400>,

			<0xb111050  0x08>,

			<0xb011050  0x08>,

			<0xb1d1050  0x08>,

			<0x00a412c  0x08>;

		reg-names = "rcgwr-c0-base", "rcgwr-c1-base",

			    "c0-pll", "c0-mux", "c1-mux",

			    "cci-mux", "efuse";

		vdd-mx-supply = <&pmtitanium_s7_level_ao>;

		vdd-cl-supply = <&apc_vreg_corner>;

		clocks = <&clock_gcc clk_xo_a_clk_src>;

		clock-names = "xo_a";

		qcom,enable-vmin;

		qcom,num-clusters = <2>;

		qcom,speed0-bin-v0-cl =

			/*            safe_L */

			<          0 0 0>,

			< 652800000  1 (-1)>,

			< 2150400000 6 102 >,

			< 2208000000 7 104 >;

		qcom,speed0-bin-v0-cci =

			<          0 0>,

			<  261120000 1>,

			<  860160000 6>,

			<  883200000 7>;

		qcom,pboost-delta = <0 50 100>;

		#address-cells = <1>;

		#size-cells = <1>;

	};

arch/arm/boot/dts/qcom/msmtitanium.dtsi

+3 −2
Original line number Diff line number Diff line
@@ -839,13 +839,14 @@ 
		compatible = "qcom,cpu-clock-titanium";

		reg =   <0xb114000  0x68>,

			<0xb014000  0x68>,

			<0xb116000  0x400>,

			<0xb116000  0x330>,

			<0xb016000  0x330>,

			<0xb111050  0x08>,

			<0xb011050  0x08>,

			<0xb1d1050  0x08>,

			<0x00a4124  0x08>;

		reg-names = "rcgwr-c0-base", "rcgwr-c1-base",

			    "c0-pll", "c0-mux", "c1-mux",

			    "c0-pll", "c1-pll", "c0-mux", "c1-mux",

			    "cci-mux", "efuse";

		vdd-mx-supply = <&pmtitanium_s7_level_ao>;

		vdd-cl-supply = <&apc_vreg>;

drivers/clk/msm/clock-cpu-titanium.c

+920 −45

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