Loading drivers/video/msm/mdss/mdss_dsi_host.c +24 −7 Original line number Diff line number Diff line Loading @@ -39,6 +39,8 @@ #define MDSS_DSI_INT_CTRL 0x0110 #define CEIL(x, y) (((x) + ((y) - 1)) / (y)) struct mdss_dsi_ctrl_pdata *ctrl_list[DSI_CTRL_MAX]; struct mdss_hw mdss_dsi0_hw = { Loading Loading @@ -2334,17 +2336,21 @@ void mdss_dsi_wait4video_done(struct mdss_dsi_ctrl_pdata *ctrl) /* DSI_INTL_CTRL */ data = MIPI_INP((ctrl->ctrl_base) + 0x0110); /* clear previous VIDEO_DONE interrupt as well */ data &= (DSI_INTR_TOTAL_MASK | DSI_INTR_VIDEO_DONE); data |= DSI_INTR_VIDEO_DONE_MASK; MIPI_OUTP((ctrl->ctrl_base) + 0x0110, data); /* clear previous VIDEO_DONE interrupt first */ data &= DSI_INTR_TOTAL_MASK; MIPI_OUTP((ctrl->ctrl_base) + 0x0110, (data | DSI_INTR_VIDEO_DONE)); wmb(); /* make sure write happened */ spin_lock_irqsave(&ctrl->mdp_lock, flag); reinit_completion(&ctrl->video_comp); mdss_dsi_enable_irq(ctrl, DSI_VIDEO_TERM); spin_unlock_irqrestore(&ctrl->mdp_lock, flag); /* set interrupt enable bit for VIDEO_DONE */ data |= DSI_INTR_VIDEO_DONE_MASK; MIPI_OUTP((ctrl->ctrl_base) + 0x0110, data); wmb(); /* make sure write happened */ wait_for_completion_timeout(&ctrl->video_comp, msecs_to_jiffies(VSYNC_PERIOD * 4)); Loading @@ -2357,14 +2363,25 @@ void mdss_dsi_wait4video_done(struct mdss_dsi_ctrl_pdata *ctrl) static int mdss_dsi_wait4video_eng_busy(struct mdss_dsi_ctrl_pdata *ctrl) { int ret = 0; u32 v_total = 0, v_blank = 0, sleep_ms = 0, fps = 0; struct mdss_panel_info *pinfo = &ctrl->panel_data.panel_info; if (ctrl->panel_mode == DSI_CMD_MODE) return ret; if (ctrl->ctrl_state & CTRL_STATE_MDP_ACTIVE) { mdss_dsi_wait4video_done(ctrl); /* delay 4 ms to skip BLLP */ usleep_range(4000, 4000); v_total = mdss_panel_get_vtotal(pinfo); v_blank = pinfo->lcdc.v_back_porch + pinfo->lcdc.v_pulse_width; if (pinfo->dynamic_fps && pinfo->current_fps) fps = pinfo->current_fps; else fps = pinfo->mipi.frame_rate; sleep_ms = CEIL((v_blank * 1000), (v_total * fps)); /* delay sleep_ms to skip BLLP */ if (sleep_ms) usleep_range((sleep_ms * 1000), (sleep_ms * 1000) + 10); ret = 1; } Loading Loading
drivers/video/msm/mdss/mdss_dsi_host.c +24 −7 Original line number Diff line number Diff line Loading @@ -39,6 +39,8 @@ #define MDSS_DSI_INT_CTRL 0x0110 #define CEIL(x, y) (((x) + ((y) - 1)) / (y)) struct mdss_dsi_ctrl_pdata *ctrl_list[DSI_CTRL_MAX]; struct mdss_hw mdss_dsi0_hw = { Loading Loading @@ -2334,17 +2336,21 @@ void mdss_dsi_wait4video_done(struct mdss_dsi_ctrl_pdata *ctrl) /* DSI_INTL_CTRL */ data = MIPI_INP((ctrl->ctrl_base) + 0x0110); /* clear previous VIDEO_DONE interrupt as well */ data &= (DSI_INTR_TOTAL_MASK | DSI_INTR_VIDEO_DONE); data |= DSI_INTR_VIDEO_DONE_MASK; MIPI_OUTP((ctrl->ctrl_base) + 0x0110, data); /* clear previous VIDEO_DONE interrupt first */ data &= DSI_INTR_TOTAL_MASK; MIPI_OUTP((ctrl->ctrl_base) + 0x0110, (data | DSI_INTR_VIDEO_DONE)); wmb(); /* make sure write happened */ spin_lock_irqsave(&ctrl->mdp_lock, flag); reinit_completion(&ctrl->video_comp); mdss_dsi_enable_irq(ctrl, DSI_VIDEO_TERM); spin_unlock_irqrestore(&ctrl->mdp_lock, flag); /* set interrupt enable bit for VIDEO_DONE */ data |= DSI_INTR_VIDEO_DONE_MASK; MIPI_OUTP((ctrl->ctrl_base) + 0x0110, data); wmb(); /* make sure write happened */ wait_for_completion_timeout(&ctrl->video_comp, msecs_to_jiffies(VSYNC_PERIOD * 4)); Loading @@ -2357,14 +2363,25 @@ void mdss_dsi_wait4video_done(struct mdss_dsi_ctrl_pdata *ctrl) static int mdss_dsi_wait4video_eng_busy(struct mdss_dsi_ctrl_pdata *ctrl) { int ret = 0; u32 v_total = 0, v_blank = 0, sleep_ms = 0, fps = 0; struct mdss_panel_info *pinfo = &ctrl->panel_data.panel_info; if (ctrl->panel_mode == DSI_CMD_MODE) return ret; if (ctrl->ctrl_state & CTRL_STATE_MDP_ACTIVE) { mdss_dsi_wait4video_done(ctrl); /* delay 4 ms to skip BLLP */ usleep_range(4000, 4000); v_total = mdss_panel_get_vtotal(pinfo); v_blank = pinfo->lcdc.v_back_porch + pinfo->lcdc.v_pulse_width; if (pinfo->dynamic_fps && pinfo->current_fps) fps = pinfo->current_fps; else fps = pinfo->mipi.frame_rate; sleep_ms = CEIL((v_blank * 1000), (v_total * fps)); /* delay sleep_ms to skip BLLP */ if (sleep_ms) usleep_range((sleep_ms * 1000), (sleep_ms * 1000) + 10); ret = 1; } Loading