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Commit 20707ad5 authored by Padmanabhan Komanduru's avatar Padmanabhan Komanduru Committed by raghavendra ambadas
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msm: mdss: update the wait sequence for DSI_VIDEO_DONE interrupt 



At present, the previous VIDEO_DONE interrupt bit is cleared and
the VIDEO_DONE_MASK bit are set in the DSI interrupt register by a
single register write operation. This seems to be not reliable
always and the DSI_VIDEO_DONE interrupt is generated for the
previous VIDEO_DONE sometimes. Fix this sequence by clearing the
previous DSI_VIDEO_DONE interrupt bit first followed by a separate
register write to enable the VIDEO_DONE_MASK bit.

Change-Id: Ic51424031bb1e4b5c5fae21bfe180c4620151c21
Signed-off-by: default avatarPadmanabhan Komanduru <pkomandu@codeaurora.org>
parent 950e16c2

drivers/video/msm/mdss/mdss_dsi_host.c

+9 −5
Original line number Diff line number Diff line
@@ -2336,17 +2336,21 @@ void mdss_dsi_wait4video_done(struct mdss_dsi_ctrl_pdata *ctrl) 


	/* DSI_INTL_CTRL */

	data = MIPI_INP((ctrl->ctrl_base) + 0x0110);

	/* clear previous VIDEO_DONE interrupt as well */

	data &= (DSI_INTR_TOTAL_MASK | DSI_INTR_VIDEO_DONE);

	data |= DSI_INTR_VIDEO_DONE_MASK;



	MIPI_OUTP((ctrl->ctrl_base) + 0x0110, data);

	/* clear previous VIDEO_DONE interrupt first */

	data &= DSI_INTR_TOTAL_MASK;

	MIPI_OUTP((ctrl->ctrl_base) + 0x0110, (data | DSI_INTR_VIDEO_DONE));

	wmb(); /* make sure write happened */



	spin_lock_irqsave(&ctrl->mdp_lock, flag);

	reinit_completion(&ctrl->video_comp);

	mdss_dsi_enable_irq(ctrl, DSI_VIDEO_TERM);

	spin_unlock_irqrestore(&ctrl->mdp_lock, flag);



	/* set interrupt enable bit for VIDEO_DONE */

	data |= DSI_INTR_VIDEO_DONE_MASK;

	MIPI_OUTP((ctrl->ctrl_base) + 0x0110, data);

	wmb(); /* make sure write happened */



	wait_for_completion_timeout(&ctrl->video_comp,

			msecs_to_jiffies(VSYNC_PERIOD * 4));