Loading Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x 0 → 100644 +450 −0 Original line number Diff line number Diff line What: /sys/bus/coresight/devices/<memory_map>.etm/enable_source Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Enable/disable tracing on this specific trace entiry. Enabling a source implies the source has been configured properly and a sink has been identidifed for it. The path of coresight components linking the source to the sink is configured and managed automatically by the coresight framework. What: /sys/bus/coresight/devices/<memory_map>.etm/cpu Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) The CPU this tracing entity is associated with. What: /sys/bus/coresight/devices/<memory_map>.etm/nr_pe_cmp Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Indicates the number of PE comparator inputs that are available for tracing. What: /sys/bus/coresight/devices/<memory_map>.etm/nr_addr_cmp Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Indicates the number of address comparator pairs that are available for tracing. What: /sys/bus/coresight/devices/<memory_map>.etm/nr_cntr Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Indicates the number of counters that are available for tracing. What: /sys/bus/coresight/devices/<memory_map>.etm/nr_ext_inp Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Indicates how many external inputs are implemented. What: /sys/bus/coresight/devices/<memory_map>.etm/numcidc Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Indicates the number of Context ID comparators that are available for tracing. What: /sys/bus/coresight/devices/<memory_map>.etm/numvmidc Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Indicates the number of VMID comparators that are available for tracing. What: /sys/bus/coresight/devices/<memory_map>.etm/nrseqstate Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Indicates the number of sequencer states that are implemented. What: /sys/bus/coresight/devices/<memory_map>.etm/nr_resource Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Indicates the number of resource selection pairs that are available for tracing. What: /sys/bus/coresight/devices/<memory_map>.etm/nr_ss_cmp Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Indicates the number of single-shot comparator controls that are available for tracing. What: /sys/bus/coresight/devices/<memory_map>.etm/reset Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (W) Cancels all configuration on a trace unit and set it back to its boot configuration. What: /sys/bus/coresight/devices/<memory_map>.etm/mode Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Controls various modes supported by this ETM, for example P0 instruction tracing, branch broadcast, cycle counting and context ID tracing. What: /sys/bus/coresight/devices/<memory_map>.etm/pe Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Controls which PE to trace. What: /sys/bus/coresight/devices/<memory_map>.etm/event Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Controls the tracing of arbitrary events from bank 0 to 3. What: /sys/bus/coresight/devices/<memory_map>.etm/event_instren Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Controls the behavior of the events in bank 0 to 3. What: /sys/bus/coresight/devices/<memory_map>.etm/event_ts Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Controls the insertion of global timestamps in the trace streams. What: /sys/bus/coresight/devices/<memory_map>.etm/syncfreq Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Controls how often trace synchronization requests occur. What: /sys/bus/coresight/devices/<memory_map>.etm/cyc_threshold Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Sets the threshold value for cycle counting. What: /sys/bus/coresight/devices/<memory_map>.etm/bb_ctrl Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Controls which regions in the memory map are enabled to use branch broadcasting. What: /sys/bus/coresight/devices/<memory_map>.etm/event_vinst Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Controls instruction trace filtering. What: /sys/bus/coresight/devices/<memory_map>.etm/s_exlevel_vinst Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) In Secure state, each bit controls whether instruction tracing is enabled for the corresponding exception level. What: /sys/bus/coresight/devices/<memory_map>.etm/ns_exlevel_vinst Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) In non-secure state, each bit controls whether instruction tracing is enabled for the corresponding exception level. What: /sys/bus/coresight/devices/<memory_map>.etm/addr_idx Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Select which address comparator or pair (of comparators) to work with. What: /sys/bus/coresight/devices/<memory_map>.etm/addr_instdatatype Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Controls what type of comparison the trace unit performs. What: /sys/bus/coresight/devices/<memory_map>.etm/addr_single Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Used to setup single address comparator values. What: /sys/bus/coresight/devices/<memory_map>.etm/addr_range Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Used to setup address range comparator values. What: /sys/bus/coresight/devices/<memory_map>.etm/seq_idx Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Select which sequensor. What: /sys/bus/coresight/devices/<memory_map>.etm/seq_state Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Use this to set, or read, the sequencer state. What: /sys/bus/coresight/devices/<memory_map>.etm/seq_event Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Moves the sequencer state to a specific state. What: /sys/bus/coresight/devices/<memory_map>.etm/seq_reset_event Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Moves the sequencer to state 0 when a programmed event occurs. What: /sys/bus/coresight/devices/<memory_map>.etm/cntr_idx Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Select which counter unit to work with. What: /sys/bus/coresight/devices/<memory_map>.etm/cntrldvr Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) This sets or returns the reload count value of the specific counter. What: /sys/bus/coresight/devices/<memory_map>.etm/cntr_val Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) This sets or returns the current count value of the specific counter. What: /sys/bus/coresight/devices/<memory_map>.etm/cntr_ctrl Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Controls the operation of the selected counter. What: /sys/bus/coresight/devices/<memory_map>.etm/res_idx Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Select which resource selection unit to work with. What: /sys/bus/coresight/devices/<memory_map>.etm/res_ctrl Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Controls the selection of the resources in the trace unit. What: /sys/bus/coresight/devices/<memory_map>.etm/ctxid_idx Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Select which context ID comparator to work with. What: /sys/bus/coresight/devices/<memory_map>.etm/ctxid_val Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Get/Set the context ID comparator value to trigger on. What: /sys/bus/coresight/devices/<memory_map>.etm/ctxid_masks Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Mask for all 8 context ID comparator value registers (if implemented). What: /sys/bus/coresight/devices/<memory_map>.etm/vmid_idx Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Select which virtual machine ID comparator to work with. What: /sys/bus/coresight/devices/<memory_map>.etm/vmid_val Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Get/Set the virtual machine ID comparator value to trigger on. What: /sys/bus/coresight/devices/<memory_map>.etm/vmid_masks Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Mask for all 8 virtual machine ID comparator value registers (if implemented). What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcoslsr Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Print the content of the OS Lock Status Register (0x304). The value it taken directly from the HW. What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpdcr Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Print the content of the Power Down Control Register (0x310). The value is taken directly from the HW. What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpdsr Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Print the content of the Power Down Status Register (0x314). The value is taken directly from the HW. What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trclsr Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Print the content of the SW Lock Status Register (0xFB4). The value is taken directly from the HW. What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcauthstatus Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Print the content of the Authentication Status Register (0xFB8). The value is taken directly from the HW. What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcdevid Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Print the content of the Device ID Register (0xFC8). The value is taken directly from the HW. What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcdevtype Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Print the content of the Device Type Register (0xFCC). The value is taken directly from the HW. What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr0 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Print the content of the Peripheral ID0 Register (0xFE0). The value is taken directly from the HW. What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr1 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Print the content of the Peripheral ID1 Register (0xFE4). The value is taken directly from the HW. What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr2 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Print the content of the Peripheral ID2 Register (0xFE8). The value is taken directly from the HW. What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr3 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Print the content of the Peripheral ID3 Register (0xFEC). The value is taken directly from the HW. What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr0 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Returns the tracing capabilities of the trace unit (0x1E0). The value is taken directly from the HW. What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr1 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Returns the tracing capabilities of the trace unit (0x1E4). The value is taken directly from the HW. What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr2 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Returns the maximum size of the data value, data address, VMID, context ID and instuction address in the trace unit (0x1E8). The value is taken directly from the HW. What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr3 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Returns the value associated with various resources available to the trace unit. See the Trace Macrocell architecture specification for more details (0x1E8). The value is taken directly from the HW. What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr4 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Returns how many resources the trace unit supports (0x1F0). The value is taken directly from the HW. What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr5 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Returns how many resources the trace unit supports (0x1F4). The value is taken directly from the HW. What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr8 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Returns the maximum speculation depth of the instruction trace stream. (0x180). The value is taken directly from the HW. What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr9 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Returns the number of P0 right-hand keys that the trace unit can use (0x184). The value is taken directly from the HW. What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr10 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Returns the number of P1 right-hand keys that the trace unit can use (0x188). The value is taken directly from the HW. What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr11 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Returns the number of special P1 right-hand keys that the trace unit can use (0x18C). The value is taken directly from the HW. What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr12 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Returns the number of conditional P1 right-hand keys that the trace unit can use (0x190). The value is taken directly from the HW. What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr13 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Returns the number of special conditional P1 right-hand keys that the trace unit can use (0x194). The value is taken directly from the HW. Documentation/devicetree/bindings/arm/coresight.txt +1 −0 Original line number Diff line number Diff line Loading @@ -17,6 +17,7 @@ its hardware characteristcs. - "arm,coresight-tmc", "arm,primecell"; - "arm,coresight-funnel", "arm,primecell"; - "arm,coresight-etm3x", "arm,primecell"; - "qcom,coresight-replicator1x", "arm,primecell"; * reg: physical base address and length of the register set(s) of the component. Loading drivers/hwtracing/coresight/Kconfig +19 −0 Original line number Diff line number Diff line Loading @@ -69,6 +69,24 @@ config CORESIGHT_SOURCE_ETM3X This is primarily useful for instruction level tracing. Depending the ETM version data tracing may also be available. config CORESIGHT_SOURCE_ETM4X bool "CoreSight Embedded Trace Macrocell 4.x driver" depends on ARM64 select CORESIGHT_LINKS_AND_SINKS help This driver provides support for the ETM4.x tracer module, tracing the instructions that a processor is executing. This is primarily useful for instruction level tracing. Depending on the implemented version data tracing may also be available. config CORESIGHT_QCOM_REPLICATOR bool "Qualcomm CoreSight Replicator driver" depends on CORESIGHT_LINKS_AND_SINKS help This enables support for Qualcomm CoreSight link driver. The programmable ATB replicator sends the ATB trace stream from the ETB/ETF to the TPIUi and ETR. config CORESIGHT_STM bool "CoreSight System Trace Macrocell driver" depends on CORESIGHT_LINKS_AND_SINKS Loading @@ -76,4 +94,5 @@ config CORESIGHT_STM This driver provides support for hardware assisted software instrumentation based tracing. This is primarily useful for logging useful software events or data. endif drivers/hwtracing/coresight/Makefile +2 −0 Original line number Diff line number Diff line Loading @@ -10,4 +10,6 @@ obj-$(CONFIG_CORESIGHT_SINK_ETBV10) += coresight-etb10.o obj-$(CONFIG_CORESIGHT_LINKS_AND_SINKS) += coresight-funnel.o \ coresight-replicator.o obj-$(CONFIG_CORESIGHT_SOURCE_ETM3X) += coresight-etm3x.o coresight-etm-cp14.o obj-$(CONFIG_CORESIGHT_SOURCE_ETM4X) += coresight-etm4x.o obj-$(CONFIG_CORESIGHT_QCOM_REPLICATOR) += coresight-replicator-qcom.o obj-$(CONFIG_CORESIGHT_STM) += coresight-stm.o drivers/hwtracing/coresight/coresight-etb10.c +46 −26 Original line number Diff line number Diff line Loading @@ -22,10 +22,11 @@ #include <linux/uaccess.h> #include <linux/slab.h> #include <linux/spinlock.h> #include <linux/clk.h> #include <linux/pm_runtime.h> #include <linux/seq_file.h> #include <linux/coresight.h> #include <linux/amba/bus.h> #include <linux/clk.h> #include "coresight-priv.h" Loading Loading @@ -66,9 +67,9 @@ * struct etb_drvdata - specifics associated to an ETB component * @base: memory mapped base address for this component. * @dev: the device entity associated to this component. * @atclk: optional clock for the core parts of the ETB. * @csdev: component vitals needed by the framework. * @miscdev: specifics to handle "/dev/xyz.etb" entry. * @clk: the clock this component is associated to. * @spinlock: only one at a time pls. * @in_use: synchronise user space access to etb buffer. * @buf: area of memory where ETB buffer content gets sent. Loading @@ -79,9 +80,9 @@ struct etb_drvdata { void __iomem *base; struct device *dev; struct clk *atclk; struct coresight_device *csdev; struct miscdevice miscdev; struct clk *clk; spinlock_t spinlock; atomic_t in_use; u8 *buf; Loading @@ -92,17 +93,14 @@ struct etb_drvdata { static unsigned int etb_get_buffer_depth(struct etb_drvdata *drvdata) { int ret; u32 depth = 0; ret = clk_prepare_enable(drvdata->clk); if (ret) return ret; pm_runtime_get_sync(drvdata->dev); /* RO registers don't need locking */ depth = readl_relaxed(drvdata->base + ETB_RAM_DEPTH_REG); clk_disable_unprepare(drvdata->clk); pm_runtime_put(drvdata->dev); return depth; } Loading Loading @@ -137,12 +135,9 @@ static void etb_enable_hw(struct etb_drvdata *drvdata) static int etb_enable(struct coresight_device *csdev) { struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); int ret; unsigned long flags; ret = clk_prepare_enable(drvdata->clk); if (ret) return ret; pm_runtime_get_sync(drvdata->dev); spin_lock_irqsave(&drvdata->spinlock, flags); etb_enable_hw(drvdata); Loading Loading @@ -252,7 +247,7 @@ static void etb_disable(struct coresight_device *csdev) drvdata->enable = false; spin_unlock_irqrestore(&drvdata->spinlock, flags); clk_disable_unprepare(drvdata->clk); pm_runtime_put(drvdata->dev); dev_info(drvdata->dev, "ETB disabled\n"); } Loading Loading @@ -339,16 +334,12 @@ static const struct file_operations etb_fops = { static ssize_t status_show(struct device *dev, struct device_attribute *attr, char *buf) { int ret; unsigned long flags; u32 etb_rdr, etb_sr, etb_rrp, etb_rwp; u32 etb_trg, etb_cr, etb_ffsr, etb_ffcr; struct etb_drvdata *drvdata = dev_get_drvdata(dev->parent); ret = clk_prepare_enable(drvdata->clk); if (ret) goto out; pm_runtime_get_sync(drvdata->dev); spin_lock_irqsave(&drvdata->spinlock, flags); CS_UNLOCK(drvdata->base); Loading @@ -364,7 +355,7 @@ static ssize_t status_show(struct device *dev, CS_LOCK(drvdata->base); spin_unlock_irqrestore(&drvdata->spinlock, flags); clk_disable_unprepare(drvdata->clk); pm_runtime_put(drvdata->dev); return sprintf(buf, "Depth:\t\t0x%x\n" Loading @@ -377,7 +368,7 @@ static ssize_t status_show(struct device *dev, "Flush ctrl:\t0x%x\n", etb_rdr, etb_sr, etb_rrp, etb_rwp, etb_trg, etb_cr, etb_ffsr, etb_ffcr); out: return -EINVAL; } static DEVICE_ATTR_RO(status); Loading Loading @@ -438,6 +429,12 @@ static int etb_probe(struct amba_device *adev, const struct amba_id *id) return -ENOMEM; drvdata->dev = &adev->dev; drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */ if (!IS_ERR(drvdata->atclk)) { ret = clk_prepare_enable(drvdata->atclk); if (ret) return ret; } dev_set_drvdata(dev, drvdata); /* validity for the resource is already checked by the AMBA core */ Loading @@ -449,13 +446,8 @@ static int etb_probe(struct amba_device *adev, const struct amba_id *id) spin_lock_init(&drvdata->spinlock); drvdata->clk = adev->pclk; ret = clk_prepare_enable(drvdata->clk); if (ret) return ret; drvdata->buffer_depth = etb_get_buffer_depth(drvdata); clk_disable_unprepare(drvdata->clk); pm_runtime_put(&adev->dev); if (drvdata->buffer_depth & 0x80000000) return -EINVAL; Loading Loading @@ -506,6 +498,32 @@ static int etb_remove(struct amba_device *adev) return 0; } #ifdef CONFIG_PM static int etb_runtime_suspend(struct device *dev) { struct etb_drvdata *drvdata = dev_get_drvdata(dev); if (drvdata && !IS_ERR(drvdata->atclk)) clk_disable_unprepare(drvdata->atclk); return 0; } static int etb_runtime_resume(struct device *dev) { struct etb_drvdata *drvdata = dev_get_drvdata(dev); if (drvdata && !IS_ERR(drvdata->atclk)) clk_prepare_enable(drvdata->atclk); return 0; } #endif static const struct dev_pm_ops etb_dev_pm_ops = { SET_RUNTIME_PM_OPS(etb_runtime_suspend, etb_runtime_resume, NULL) }; static struct amba_id etb_ids[] = { { .id = 0x0003b907, Loading @@ -518,6 +536,8 @@ static struct amba_driver etb_driver = { .drv = { .name = "coresight-etb10", .owner = THIS_MODULE, .pm = &etb_dev_pm_ops, }, .probe = etb_probe, .remove = etb_remove, Loading Loading
Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x 0 → 100644 +450 −0 Original line number Diff line number Diff line What: /sys/bus/coresight/devices/<memory_map>.etm/enable_source Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Enable/disable tracing on this specific trace entiry. Enabling a source implies the source has been configured properly and a sink has been identidifed for it. The path of coresight components linking the source to the sink is configured and managed automatically by the coresight framework. What: /sys/bus/coresight/devices/<memory_map>.etm/cpu Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) The CPU this tracing entity is associated with. What: /sys/bus/coresight/devices/<memory_map>.etm/nr_pe_cmp Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Indicates the number of PE comparator inputs that are available for tracing. What: /sys/bus/coresight/devices/<memory_map>.etm/nr_addr_cmp Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Indicates the number of address comparator pairs that are available for tracing. What: /sys/bus/coresight/devices/<memory_map>.etm/nr_cntr Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Indicates the number of counters that are available for tracing. What: /sys/bus/coresight/devices/<memory_map>.etm/nr_ext_inp Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Indicates how many external inputs are implemented. What: /sys/bus/coresight/devices/<memory_map>.etm/numcidc Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Indicates the number of Context ID comparators that are available for tracing. What: /sys/bus/coresight/devices/<memory_map>.etm/numvmidc Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Indicates the number of VMID comparators that are available for tracing. What: /sys/bus/coresight/devices/<memory_map>.etm/nrseqstate Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Indicates the number of sequencer states that are implemented. What: /sys/bus/coresight/devices/<memory_map>.etm/nr_resource Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Indicates the number of resource selection pairs that are available for tracing. What: /sys/bus/coresight/devices/<memory_map>.etm/nr_ss_cmp Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Indicates the number of single-shot comparator controls that are available for tracing. What: /sys/bus/coresight/devices/<memory_map>.etm/reset Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (W) Cancels all configuration on a trace unit and set it back to its boot configuration. What: /sys/bus/coresight/devices/<memory_map>.etm/mode Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Controls various modes supported by this ETM, for example P0 instruction tracing, branch broadcast, cycle counting and context ID tracing. What: /sys/bus/coresight/devices/<memory_map>.etm/pe Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Controls which PE to trace. What: /sys/bus/coresight/devices/<memory_map>.etm/event Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Controls the tracing of arbitrary events from bank 0 to 3. What: /sys/bus/coresight/devices/<memory_map>.etm/event_instren Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Controls the behavior of the events in bank 0 to 3. What: /sys/bus/coresight/devices/<memory_map>.etm/event_ts Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Controls the insertion of global timestamps in the trace streams. What: /sys/bus/coresight/devices/<memory_map>.etm/syncfreq Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Controls how often trace synchronization requests occur. What: /sys/bus/coresight/devices/<memory_map>.etm/cyc_threshold Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Sets the threshold value for cycle counting. What: /sys/bus/coresight/devices/<memory_map>.etm/bb_ctrl Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Controls which regions in the memory map are enabled to use branch broadcasting. What: /sys/bus/coresight/devices/<memory_map>.etm/event_vinst Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Controls instruction trace filtering. What: /sys/bus/coresight/devices/<memory_map>.etm/s_exlevel_vinst Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) In Secure state, each bit controls whether instruction tracing is enabled for the corresponding exception level. What: /sys/bus/coresight/devices/<memory_map>.etm/ns_exlevel_vinst Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) In non-secure state, each bit controls whether instruction tracing is enabled for the corresponding exception level. What: /sys/bus/coresight/devices/<memory_map>.etm/addr_idx Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Select which address comparator or pair (of comparators) to work with. What: /sys/bus/coresight/devices/<memory_map>.etm/addr_instdatatype Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Controls what type of comparison the trace unit performs. What: /sys/bus/coresight/devices/<memory_map>.etm/addr_single Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Used to setup single address comparator values. What: /sys/bus/coresight/devices/<memory_map>.etm/addr_range Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Used to setup address range comparator values. What: /sys/bus/coresight/devices/<memory_map>.etm/seq_idx Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Select which sequensor. What: /sys/bus/coresight/devices/<memory_map>.etm/seq_state Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Use this to set, or read, the sequencer state. What: /sys/bus/coresight/devices/<memory_map>.etm/seq_event Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Moves the sequencer state to a specific state. What: /sys/bus/coresight/devices/<memory_map>.etm/seq_reset_event Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Moves the sequencer to state 0 when a programmed event occurs. What: /sys/bus/coresight/devices/<memory_map>.etm/cntr_idx Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Select which counter unit to work with. What: /sys/bus/coresight/devices/<memory_map>.etm/cntrldvr Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) This sets or returns the reload count value of the specific counter. What: /sys/bus/coresight/devices/<memory_map>.etm/cntr_val Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) This sets or returns the current count value of the specific counter. What: /sys/bus/coresight/devices/<memory_map>.etm/cntr_ctrl Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Controls the operation of the selected counter. What: /sys/bus/coresight/devices/<memory_map>.etm/res_idx Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Select which resource selection unit to work with. What: /sys/bus/coresight/devices/<memory_map>.etm/res_ctrl Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Controls the selection of the resources in the trace unit. What: /sys/bus/coresight/devices/<memory_map>.etm/ctxid_idx Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Select which context ID comparator to work with. What: /sys/bus/coresight/devices/<memory_map>.etm/ctxid_val Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Get/Set the context ID comparator value to trigger on. What: /sys/bus/coresight/devices/<memory_map>.etm/ctxid_masks Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Mask for all 8 context ID comparator value registers (if implemented). What: /sys/bus/coresight/devices/<memory_map>.etm/vmid_idx Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Select which virtual machine ID comparator to work with. What: /sys/bus/coresight/devices/<memory_map>.etm/vmid_val Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Get/Set the virtual machine ID comparator value to trigger on. What: /sys/bus/coresight/devices/<memory_map>.etm/vmid_masks Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Mask for all 8 virtual machine ID comparator value registers (if implemented). What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcoslsr Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Print the content of the OS Lock Status Register (0x304). The value it taken directly from the HW. What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpdcr Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Print the content of the Power Down Control Register (0x310). The value is taken directly from the HW. What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpdsr Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Print the content of the Power Down Status Register (0x314). The value is taken directly from the HW. What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trclsr Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Print the content of the SW Lock Status Register (0xFB4). The value is taken directly from the HW. What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcauthstatus Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Print the content of the Authentication Status Register (0xFB8). The value is taken directly from the HW. What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcdevid Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Print the content of the Device ID Register (0xFC8). The value is taken directly from the HW. What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcdevtype Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Print the content of the Device Type Register (0xFCC). The value is taken directly from the HW. What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr0 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Print the content of the Peripheral ID0 Register (0xFE0). The value is taken directly from the HW. What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr1 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Print the content of the Peripheral ID1 Register (0xFE4). The value is taken directly from the HW. What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr2 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Print the content of the Peripheral ID2 Register (0xFE8). The value is taken directly from the HW. What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr3 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Print the content of the Peripheral ID3 Register (0xFEC). The value is taken directly from the HW. What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr0 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Returns the tracing capabilities of the trace unit (0x1E0). The value is taken directly from the HW. What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr1 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Returns the tracing capabilities of the trace unit (0x1E4). The value is taken directly from the HW. What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr2 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Returns the maximum size of the data value, data address, VMID, context ID and instuction address in the trace unit (0x1E8). The value is taken directly from the HW. What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr3 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Returns the value associated with various resources available to the trace unit. See the Trace Macrocell architecture specification for more details (0x1E8). The value is taken directly from the HW. What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr4 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Returns how many resources the trace unit supports (0x1F0). The value is taken directly from the HW. What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr5 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Returns how many resources the trace unit supports (0x1F4). The value is taken directly from the HW. What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr8 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Returns the maximum speculation depth of the instruction trace stream. (0x180). The value is taken directly from the HW. What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr9 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Returns the number of P0 right-hand keys that the trace unit can use (0x184). The value is taken directly from the HW. What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr10 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Returns the number of P1 right-hand keys that the trace unit can use (0x188). The value is taken directly from the HW. What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr11 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Returns the number of special P1 right-hand keys that the trace unit can use (0x18C). The value is taken directly from the HW. What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr12 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Returns the number of conditional P1 right-hand keys that the trace unit can use (0x190). The value is taken directly from the HW. What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr13 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Returns the number of special conditional P1 right-hand keys that the trace unit can use (0x194). The value is taken directly from the HW.
Documentation/devicetree/bindings/arm/coresight.txt +1 −0 Original line number Diff line number Diff line Loading @@ -17,6 +17,7 @@ its hardware characteristcs. - "arm,coresight-tmc", "arm,primecell"; - "arm,coresight-funnel", "arm,primecell"; - "arm,coresight-etm3x", "arm,primecell"; - "qcom,coresight-replicator1x", "arm,primecell"; * reg: physical base address and length of the register set(s) of the component. Loading
drivers/hwtracing/coresight/Kconfig +19 −0 Original line number Diff line number Diff line Loading @@ -69,6 +69,24 @@ config CORESIGHT_SOURCE_ETM3X This is primarily useful for instruction level tracing. Depending the ETM version data tracing may also be available. config CORESIGHT_SOURCE_ETM4X bool "CoreSight Embedded Trace Macrocell 4.x driver" depends on ARM64 select CORESIGHT_LINKS_AND_SINKS help This driver provides support for the ETM4.x tracer module, tracing the instructions that a processor is executing. This is primarily useful for instruction level tracing. Depending on the implemented version data tracing may also be available. config CORESIGHT_QCOM_REPLICATOR bool "Qualcomm CoreSight Replicator driver" depends on CORESIGHT_LINKS_AND_SINKS help This enables support for Qualcomm CoreSight link driver. The programmable ATB replicator sends the ATB trace stream from the ETB/ETF to the TPIUi and ETR. config CORESIGHT_STM bool "CoreSight System Trace Macrocell driver" depends on CORESIGHT_LINKS_AND_SINKS Loading @@ -76,4 +94,5 @@ config CORESIGHT_STM This driver provides support for hardware assisted software instrumentation based tracing. This is primarily useful for logging useful software events or data. endif
drivers/hwtracing/coresight/Makefile +2 −0 Original line number Diff line number Diff line Loading @@ -10,4 +10,6 @@ obj-$(CONFIG_CORESIGHT_SINK_ETBV10) += coresight-etb10.o obj-$(CONFIG_CORESIGHT_LINKS_AND_SINKS) += coresight-funnel.o \ coresight-replicator.o obj-$(CONFIG_CORESIGHT_SOURCE_ETM3X) += coresight-etm3x.o coresight-etm-cp14.o obj-$(CONFIG_CORESIGHT_SOURCE_ETM4X) += coresight-etm4x.o obj-$(CONFIG_CORESIGHT_QCOM_REPLICATOR) += coresight-replicator-qcom.o obj-$(CONFIG_CORESIGHT_STM) += coresight-stm.o
drivers/hwtracing/coresight/coresight-etb10.c +46 −26 Original line number Diff line number Diff line Loading @@ -22,10 +22,11 @@ #include <linux/uaccess.h> #include <linux/slab.h> #include <linux/spinlock.h> #include <linux/clk.h> #include <linux/pm_runtime.h> #include <linux/seq_file.h> #include <linux/coresight.h> #include <linux/amba/bus.h> #include <linux/clk.h> #include "coresight-priv.h" Loading Loading @@ -66,9 +67,9 @@ * struct etb_drvdata - specifics associated to an ETB component * @base: memory mapped base address for this component. * @dev: the device entity associated to this component. * @atclk: optional clock for the core parts of the ETB. * @csdev: component vitals needed by the framework. * @miscdev: specifics to handle "/dev/xyz.etb" entry. * @clk: the clock this component is associated to. * @spinlock: only one at a time pls. * @in_use: synchronise user space access to etb buffer. * @buf: area of memory where ETB buffer content gets sent. Loading @@ -79,9 +80,9 @@ struct etb_drvdata { void __iomem *base; struct device *dev; struct clk *atclk; struct coresight_device *csdev; struct miscdevice miscdev; struct clk *clk; spinlock_t spinlock; atomic_t in_use; u8 *buf; Loading @@ -92,17 +93,14 @@ struct etb_drvdata { static unsigned int etb_get_buffer_depth(struct etb_drvdata *drvdata) { int ret; u32 depth = 0; ret = clk_prepare_enable(drvdata->clk); if (ret) return ret; pm_runtime_get_sync(drvdata->dev); /* RO registers don't need locking */ depth = readl_relaxed(drvdata->base + ETB_RAM_DEPTH_REG); clk_disable_unprepare(drvdata->clk); pm_runtime_put(drvdata->dev); return depth; } Loading Loading @@ -137,12 +135,9 @@ static void etb_enable_hw(struct etb_drvdata *drvdata) static int etb_enable(struct coresight_device *csdev) { struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); int ret; unsigned long flags; ret = clk_prepare_enable(drvdata->clk); if (ret) return ret; pm_runtime_get_sync(drvdata->dev); spin_lock_irqsave(&drvdata->spinlock, flags); etb_enable_hw(drvdata); Loading Loading @@ -252,7 +247,7 @@ static void etb_disable(struct coresight_device *csdev) drvdata->enable = false; spin_unlock_irqrestore(&drvdata->spinlock, flags); clk_disable_unprepare(drvdata->clk); pm_runtime_put(drvdata->dev); dev_info(drvdata->dev, "ETB disabled\n"); } Loading Loading @@ -339,16 +334,12 @@ static const struct file_operations etb_fops = { static ssize_t status_show(struct device *dev, struct device_attribute *attr, char *buf) { int ret; unsigned long flags; u32 etb_rdr, etb_sr, etb_rrp, etb_rwp; u32 etb_trg, etb_cr, etb_ffsr, etb_ffcr; struct etb_drvdata *drvdata = dev_get_drvdata(dev->parent); ret = clk_prepare_enable(drvdata->clk); if (ret) goto out; pm_runtime_get_sync(drvdata->dev); spin_lock_irqsave(&drvdata->spinlock, flags); CS_UNLOCK(drvdata->base); Loading @@ -364,7 +355,7 @@ static ssize_t status_show(struct device *dev, CS_LOCK(drvdata->base); spin_unlock_irqrestore(&drvdata->spinlock, flags); clk_disable_unprepare(drvdata->clk); pm_runtime_put(drvdata->dev); return sprintf(buf, "Depth:\t\t0x%x\n" Loading @@ -377,7 +368,7 @@ static ssize_t status_show(struct device *dev, "Flush ctrl:\t0x%x\n", etb_rdr, etb_sr, etb_rrp, etb_rwp, etb_trg, etb_cr, etb_ffsr, etb_ffcr); out: return -EINVAL; } static DEVICE_ATTR_RO(status); Loading Loading @@ -438,6 +429,12 @@ static int etb_probe(struct amba_device *adev, const struct amba_id *id) return -ENOMEM; drvdata->dev = &adev->dev; drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */ if (!IS_ERR(drvdata->atclk)) { ret = clk_prepare_enable(drvdata->atclk); if (ret) return ret; } dev_set_drvdata(dev, drvdata); /* validity for the resource is already checked by the AMBA core */ Loading @@ -449,13 +446,8 @@ static int etb_probe(struct amba_device *adev, const struct amba_id *id) spin_lock_init(&drvdata->spinlock); drvdata->clk = adev->pclk; ret = clk_prepare_enable(drvdata->clk); if (ret) return ret; drvdata->buffer_depth = etb_get_buffer_depth(drvdata); clk_disable_unprepare(drvdata->clk); pm_runtime_put(&adev->dev); if (drvdata->buffer_depth & 0x80000000) return -EINVAL; Loading Loading @@ -506,6 +498,32 @@ static int etb_remove(struct amba_device *adev) return 0; } #ifdef CONFIG_PM static int etb_runtime_suspend(struct device *dev) { struct etb_drvdata *drvdata = dev_get_drvdata(dev); if (drvdata && !IS_ERR(drvdata->atclk)) clk_disable_unprepare(drvdata->atclk); return 0; } static int etb_runtime_resume(struct device *dev) { struct etb_drvdata *drvdata = dev_get_drvdata(dev); if (drvdata && !IS_ERR(drvdata->atclk)) clk_prepare_enable(drvdata->atclk); return 0; } #endif static const struct dev_pm_ops etb_dev_pm_ops = { SET_RUNTIME_PM_OPS(etb_runtime_suspend, etb_runtime_resume, NULL) }; static struct amba_id etb_ids[] = { { .id = 0x0003b907, Loading @@ -518,6 +536,8 @@ static struct amba_driver etb_driver = { .drv = { .name = "coresight-etb10", .owner = THIS_MODULE, .pm = &etb_dev_pm_ops, }, .probe = etb_probe, .remove = etb_remove, Loading
