Loading drivers/gpu/msm/adreno_a5xx.c +4 −1 Original line number Diff line number Diff line Loading @@ -1020,8 +1020,11 @@ static const struct kgsl_hwcg_reg a50x_hwcg_regs[] = { {A5XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, {A5XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, {A5XX_RBBM_CLOCK_DELAY3_TP0, 0x00001111}, {A5XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222}, {A5XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222}, {A5XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222}, {A5XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, {A5XX_RBBM_CLOCK_HYST_UCHE, 0x00444444}, {A5XX_RBBM_CLOCK_HYST_UCHE, 0x00FFFFF4}, {A5XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, {A5XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, {A5XX_RBBM_CLOCK_CNTL2_RB0, 0x00222222}, Loading Loading
drivers/gpu/msm/adreno_a5xx.c +4 −1 Original line number Diff line number Diff line Loading @@ -1020,8 +1020,11 @@ static const struct kgsl_hwcg_reg a50x_hwcg_regs[] = { {A5XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, {A5XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, {A5XX_RBBM_CLOCK_DELAY3_TP0, 0x00001111}, {A5XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222}, {A5XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222}, {A5XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222}, {A5XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, {A5XX_RBBM_CLOCK_HYST_UCHE, 0x00444444}, {A5XX_RBBM_CLOCK_HYST_UCHE, 0x00FFFFF4}, {A5XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, {A5XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, {A5XX_RBBM_CLOCK_CNTL2_RB0, 0x00222222}, Loading