Merge "mhi: core: Flush M3 write" (6cb44d3e) · Commits · e / devices / android_kernel_xiaomi_markw

drivers/platform/msm/mhi/mhi_init.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -209,6 +209,7 @@ static enum MHI_STATUS mhi_init_device_ctrl(struct mhi_device_ctxt
		return MHI_STATUS_ERROR;

		mhi_dev_ctxt->enable_lpm = 1;
		mhi_dev_ctxt->flags.mhi_initialized = 0;

		mhi_log(MHI_MSG_INFO, "Allocating control segment.\n");
		ctrl_seg_size += sizeof(struct mhi_control_seg);

drivers/platform/msm/mhi/mhi_isr.c

+2 −0

Original line number	Diff line number	Diff line
		@@ -260,8 +260,10 @@ int parse_event_thread(void *ctxt)
		struct mhi_result mhi_poll(struct mhi_client_handle client_handle)
		{
		enum MHI_STATUS ret_val;

		client_handle->result.payload_buf = 0;
		client_handle->result.bytes_xferd = 0;
		client_handle->result.transaction_status = 0;
		ret_val = mhi_process_event_ring(client_handle->mhi_dev_ctxt,
		client_handle->event_ring_index,
		1);

drivers/platform/msm/mhi/mhi_states.c

+27 −29

Original line number	Diff line number	Diff line
		@@ -17,6 +17,25 @@
		#include <linux/platform_device.h>
		#include <linux/pm_runtime.h>

		static inline void mhi_set_m_state(struct mhi_device_ctxt *mhi_dev_ctxt,
		enum MHI_STATE new_state)
		{
		if (MHI_STATE_RESET == new_state) {
		mhi_reg_write_field(mhi_dev_ctxt,
		mhi_dev_ctxt->mmio_info.mmio_addr, MHICTRL,
		MHICTRL_RESET_MASK,
		MHICTRL_RESET_SHIFT,
		1);
		} else {
		mhi_reg_write_field(mhi_dev_ctxt,
		mhi_dev_ctxt->mmio_info.mmio_addr, MHICTRL,
		MHICTRL_MHISTATE_MASK,
		MHICTRL_MHISTATE_SHIFT,
		new_state);
		}
		mhi_reg_read(mhi_dev_ctxt->mmio_info.mmio_addr, MHICTRL);
		}

		static void conditional_chan_db_write(
		struct mhi_device_ctxt *mhi_dev_ctxt, u32 chan)
		{
		@@ -159,12 +178,10 @@ static enum MHI_STATUS process_m0_transition(
		atomic_set(&mhi_dev_ctxt->flags.pending_powerup, 0);
		}
		wake_up_interruptible(mhi_dev_ctxt->mhi_ev_wq.m0_event);
		if (ret_val == -ERESTARTSYS)
		mhi_log(MHI_MSG_CRITICAL,
		"Pending restart detected\n");
		write_lock_irqsave(&mhi_dev_ctxt->xfer_lock, flags);
		if ((!mhi_dev_ctxt->flags.pending_M3) &&
		(mhi_dev_ctxt->flags.link_up))
		if (!mhi_dev_ctxt->flags.pending_M3 &&
		mhi_dev_ctxt->flags.link_up &&
		mhi_dev_ctxt->flags.mhi_initialized)
		mhi_deassert_device_wake(mhi_dev_ctxt);
		write_unlock_irqrestore(&mhi_dev_ctxt->xfer_lock, flags);

		@@ -189,12 +206,7 @@ static enum MHI_STATUS process_m1_transition(
		atomic_inc(&mhi_dev_ctxt->flags.m2_transition);
		mhi_dev_ctxt->mhi_state = MHI_STATE_M2;
		mhi_log(MHI_MSG_INFO, "Allowing transition to M2\n");
		mhi_reg_write_field(mhi_dev_ctxt,
		mhi_dev_ctxt->mmio_info.mmio_addr, MHICTRL,
		MHICTRL_MHISTATE_MASK,
		MHICTRL_MHISTATE_SHIFT,
		MHI_STATE_M2);
		mhi_reg_read(mhi_dev_ctxt->mmio_info.mmio_addr, MHICTRL);
		mhi_set_m_state(mhi_dev_ctxt, MHI_STATE_M2);
		mhi_dev_ctxt->counters.m1_m2++;
		}
		write_unlock_irqrestore(&mhi_dev_ctxt->xfer_lock, flags);
		@@ -376,6 +388,7 @@ static enum MHI_STATUS process_ready_transition(
		}

		mhi_dev_ctxt->flags.stop_threads = 0;
		mhi_assert_device_wake(mhi_dev_ctxt);
		mhi_reg_write_field(mhi_dev_ctxt,
		mhi_dev_ctxt->mmio_info.mmio_addr, MHICTRL,
		MHICTRL_MHISTATE_MASK,
		@@ -600,28 +613,13 @@ static enum MHI_STATUS process_amss_transition(
		ring_all_chan_dbs(mhi_dev_ctxt);
		}
		atomic_dec(&mhi_dev_ctxt->flags.data_pending);
		if (!mhi_dev_ctxt->flags.pending_M3 &&
		mhi_dev_ctxt->flags.link_up)
		mhi_deassert_device_wake(mhi_dev_ctxt);
		mhi_log(MHI_MSG_INFO, "Exited\n");
		return MHI_STATUS_SUCCESS;
		}

		static void mhi_set_m_state(struct mhi_device_ctxt *mhi_dev_ctxt,
		enum MHI_STATE new_state)
		{
		if (MHI_STATE_RESET == new_state) {
		mhi_reg_write_field(mhi_dev_ctxt,
		mhi_dev_ctxt->mmio_info.mmio_addr, MHICTRL,
		MHICTRL_RESET_MASK,
		MHICTRL_RESET_SHIFT,
		1);
		} else {
		mhi_reg_write_field(mhi_dev_ctxt,
		mhi_dev_ctxt->mmio_info.mmio_addr, MHICTRL,
		MHICTRL_MHISTATE_MASK,
		MHICTRL_MHISTATE_SHIFT,
		new_state);
		}
		}

		enum MHI_STATUS mhi_trigger_reset(struct mhi_device_ctxt *mhi_dev_ctxt)
		{
		enum MHI_STATUS ret_val;