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Commit 6b262bf1 authored by Kukjin Kim's avatar Kukjin Kim
Browse files

Merge branch 'for_3.16/clk_fixes_non_critical' of... 

Merge branch 'for_3.16/clk_fixes_non_critical' of git://git.kernel.org/pub/scm/linux/kernel/git/tfiga/samsung-clk

 into v3.16-next/clk-samsung

Pull Samsung clock non-critical fixes from Tomasz Figa:

"This pull requests contains a number of non-critical fixes for Samsung clock
framework and drivers, including:

1) a series of fixes for Exynos5420 to correct clock definitions and make the
driver closer to the documentation,

2) several missing clocks and clock IDs added to Exynos4, Exynos5250 and
Exynos5420 drivers,

3) fix for incorrect initialization of clock table with NULL,

4) compiler warning fix."

Acked-by: default avatarMike Turquette <mturquette@linaro.org>
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parents 4b2f5cd0 77342432

arch/arm/boot/dts/exynos5420.dtsi

+7 −7
Original line number Diff line number Diff line
@@ -549,7 +549,7 @@ 
		#size-cells = <0>;

		pinctrl-names = "default";

		pinctrl-0 = <&i2c4_hs_bus>;

		clocks = <&clock CLK_I2C4>;

		clocks = <&clock CLK_USI0>;

		clock-names = "hsi2c";

		status = "disabled";

	};
@@ -562,7 +562,7 @@ 
		#size-cells = <0>;

		pinctrl-names = "default";

		pinctrl-0 = <&i2c5_hs_bus>;

		clocks = <&clock CLK_I2C5>;

		clocks = <&clock CLK_USI1>;

		clock-names = "hsi2c";

		status = "disabled";

	};
@@ -575,7 +575,7 @@ 
		#size-cells = <0>;

		pinctrl-names = "default";

		pinctrl-0 = <&i2c6_hs_bus>;

		clocks = <&clock CLK_I2C6>;

		clocks = <&clock CLK_USI2>;

		clock-names = "hsi2c";

		status = "disabled";

	};
@@ -588,7 +588,7 @@ 
		#size-cells = <0>;

		pinctrl-names = "default";

		pinctrl-0 = <&i2c7_hs_bus>;

		clocks = <&clock CLK_I2C7>;

		clocks = <&clock CLK_USI3>;

		clock-names = "hsi2c";

		status = "disabled";

	};
@@ -601,7 +601,7 @@ 
		#size-cells = <0>;

		pinctrl-names = "default";

		pinctrl-0 = <&i2c8_hs_bus>;

		clocks = <&clock CLK_I2C8>;

		clocks = <&clock CLK_USI4>;

		clock-names = "hsi2c";

		status = "disabled";

	};
@@ -614,7 +614,7 @@ 
		#size-cells = <0>;

		pinctrl-names = "default";

		pinctrl-0 = <&i2c9_hs_bus>;

		clocks = <&clock CLK_I2C9>;

		clocks = <&clock CLK_USI5>;

		clock-names = "hsi2c";

		status = "disabled";

	};
@@ -627,7 +627,7 @@ 
		#size-cells = <0>;

		pinctrl-names = "default";

		pinctrl-0 = <&i2c10_hs_bus>;

		clocks = <&clock CLK_I2C10>;

		clocks = <&clock CLK_USI6>;

		clock-names = "hsi2c";

		status = "disabled";

	};

drivers/clk/samsung/clk-exynos4.c

+2 −2
Original line number Diff line number Diff line
@@ -428,7 +428,7 @@ static struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata 
/* fixed rate clocks generated inside the soc */

static struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = {

	FRATE(0, "sclk_hdmi24m", NULL, CLK_IS_ROOT, 24000000),

	FRATE(0, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000),

	FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000),

	FRATE(0, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000),

};
@@ -903,7 +903,7 @@ static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = { 
	GATE(CLK_AUDSS, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0),

	GATE(CLK_MDNIE0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0),

	GATE(CLK_ROTATOR, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0),

	GATE(CLK_MDMA2, "mdma2", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0),

	GATE(CLK_MDMA, "mdma", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0),

	GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0,

		0),

	GATE(CLK_MIPI_HSI, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0),

drivers/clk/samsung/clk-exynos5250.c

+15 −1
Original line number Diff line number Diff line
@@ -37,6 +37,7 @@ 
#define VPLL_CON0		0x10140

#define GPLL_CON0		0x10150

#define SRC_TOP0		0x10210

#define SRC_TOP1		0x10214

#define SRC_TOP2		0x10218

#define SRC_TOP3		0x1021c

#define SRC_GSCL		0x10220
@@ -71,6 +72,7 @@ 
#define GATE_IP_GSCL		0x10920

#define GATE_IP_DISP1		0x10928

#define GATE_IP_MFC		0x1092c

#define GATE_IP_G3D		0x10930

#define GATE_IP_GEN		0x10934

#define GATE_IP_FSYS		0x10944

#define GATE_IP_PERIC		0x10950
@@ -100,6 +102,7 @@ static unsigned long exynos5250_clk_regs[] __initdata = { 
	DIV_CPU0,

	SRC_CORE1,

	SRC_TOP0,

	SRC_TOP1,

	SRC_TOP2,

	SRC_TOP3,

	SRC_GSCL,
@@ -133,6 +136,7 @@ static unsigned long exynos5250_clk_regs[] __initdata = { 
	DIV_PERIC5,

	GATE_IP_GSCL,

	GATE_IP_MFC,

	GATE_IP_G3D,

	GATE_IP_GEN,

	GATE_IP_FSYS,

	GATE_IP_PERIC,
@@ -189,10 +193,12 @@ PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi27m" }; 
PNAME(mout_vpll_p)	= { "mout_vpllsrc", "fout_vpll" };

PNAME(mout_cpll_p)	= { "fin_pll", "fout_cpll" };

PNAME(mout_epll_p)	= { "fin_pll", "fout_epll" };

PNAME(mout_gpll_p)	= { "fin_pll", "fout_gpll" };

PNAME(mout_mpll_user_p)	= { "fin_pll", "mout_mpll" };

PNAME(mout_bpll_user_p)	= { "fin_pll", "mout_bpll" };

PNAME(mout_aclk166_p)	= { "mout_cpll", "mout_mpll_user" };

PNAME(mout_aclk200_p)	= { "mout_mpll_user", "mout_bpll_user" };

PNAME(mout_aclk400_p)	= { "mout_aclk400_g3d_mid", "mout_gpll" };

PNAME(mout_aclk200_sub_p) = { "fin_pll", "div_aclk200" };

PNAME(mout_aclk266_sub_p) = { "fin_pll", "div_aclk266" };

PNAME(mout_aclk333_sub_p) = { "fin_pll", "div_aclk333" };
@@ -273,12 +279,16 @@ static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = { 
	MUX(0, "mout_aclk166", mout_aclk166_p, SRC_TOP0, 8, 1),

	MUX(0, "mout_aclk200", mout_aclk200_p, SRC_TOP0, 12, 1),

	MUX(0, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1),

	MUX(0, "mout_aclk400_g3d_mid", mout_aclk200_p, SRC_TOP0, 20, 1),



	MUX(0, "mout_aclk400_g3d", mout_aclk400_p, SRC_TOP1, 28, 1),



	MUX(0, "mout_cpll", mout_cpll_p, SRC_TOP2, 8, 1),

	MUX(0, "mout_epll", mout_epll_p, SRC_TOP2, 12, 1),

	MUX(0, "mout_vpll", mout_vpll_p, SRC_TOP2, 16, 1),

	MUX(0, "mout_mpll_user", mout_mpll_user_p, SRC_TOP2, 20, 1),

	MUX(0, "mout_bpll_user", mout_bpll_user_p, SRC_TOP2, 24, 1),

	MUX(CLK_MOUT_GPLL, "mout_gpll", mout_gpll_p, SRC_TOP2, 28, 1),



	MUX(0, "mout_aclk200_disp1_sub", mout_aclk200_sub_p, SRC_TOP3, 4, 1),

	MUX(0, "mout_aclk266_gscl_sub", mout_aclk266_sub_p, SRC_TOP3, 8, 1),
@@ -351,6 +361,8 @@ static struct samsung_div_clock exynos5250_div_clks[] __initdata = { 
	DIV(0, "div_aclk200", "mout_aclk200", DIV_TOP0, 12, 3),

	DIV(0, "div_aclk266", "mout_mpll_user", DIV_TOP0, 16, 3),

	DIV(0, "div_aclk333", "mout_aclk333", DIV_TOP0, 20, 3),

	DIV(0, "div_aclk400_g3d", "mout_aclk400_g3d", DIV_TOP0,

							24, 3),



	DIV(0, "div_aclk66_pre", "mout_mpll_user", DIV_TOP1, 24, 3),
@@ -428,6 +440,7 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = { 
	 * CMU_ACP

	 */

	GATE(CLK_MDMA0, "mdma0", "div_aclk266", GATE_IP_ACP, 1, 0, 0),

	GATE(CLK_SSS, "sss", "div_aclk266", GATE_IP_ACP, 2, 0, 0),

	GATE(CLK_G2D, "g2d", "div_aclk200", GATE_IP_ACP, 3, 0, 0),

	GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "div_aclk266", GATE_IP_ACP, 5, 0, 0),
@@ -533,7 +546,8 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = { 
		0),

	GATE(CLK_SMMU_MFCL, "smmu_mfcl", "mout_aclk333_sub", GATE_IP_MFC, 2, 0,

		0),



	GATE(CLK_G3D, "g3d", "div_aclk400_g3d", GATE_IP_G3D, 0,

					CLK_SET_RATE_PARENT, 0),

	GATE(CLK_ROTATOR, "rotator", "div_aclk266", GATE_IP_GEN, 1, 0, 0),

	GATE(CLK_JPEG, "jpeg", "div_aclk166", GATE_IP_GEN, 2, 0, 0),

	GATE(CLK_MDMA1, "mdma1", "div_aclk266", GATE_IP_GEN, 4, 0, 0),

drivers/clk/samsung/clk-exynos5420.c

+542 −312

File changed.

Preview size limit exceeded, changes collapsed.

drivers/clk/samsung/clk.c

+7 −2
Original line number Diff line number Diff line
@@ -54,14 +54,19 @@ struct samsung_clk_provider *__init samsung_clk_init(struct device_node *np, 
	struct samsung_clk_provider *ctx;

	struct clk **clk_table;

	int ret;

	int i;



	ctx = kzalloc(sizeof(struct samsung_clk_provider), GFP_KERNEL);

	if (!ctx)

		panic("could not allocate clock provider context.\n");



	clk_table = kzalloc(sizeof(struct clk *) * nr_clks, GFP_KERNEL);

	clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL);

	if (!clk_table)

		panic("could not allocate clock lookup table\n");



	for (i = 0; i < nr_clks; ++i)

		clk_table[i] = ERR_PTR(-ENOENT);



	ctx->reg_base = base;

	ctx->clk_data.clks = clk_table;

	ctx->clk_data.clk_num = nr_clks;
@@ -288,7 +293,7 @@ void __init samsung_clk_of_register_fixed_ext(struct samsung_clk_provider *ctx, 
	for_each_matching_node_and_match(clk_np, clk_matches, &match) {

		if (of_property_read_u32(clk_np, "clock-frequency", &freq))

			continue;

		fixed_rate_clk[(u32)match->data].fixed_rate = freq;

		fixed_rate_clk[(unsigned long)match->data].fixed_rate = freq;

	}

	samsung_clk_register_fixed_rate(ctx, fixed_rate_clk, nr_fixed_rate_clk);

}