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Commit 4b2f5cd0 authored by Kukjin Kim's avatar Kukjin Kim
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Merge branch 'for_3.16/exynos5260' of... 

Merge branch 'for_3.16/exynos5260' of git://git.kernel.org/pub/scm/linux/kernel/git/tfiga/samsung-clk

 into v3.16-next/clk-samsung

Pull Samsung clock exynos5260 from Tomasz Figa:

"This pull request contains patches preparing Samsung Common Clock Framework
helpers to support Exynos5260 by adding support for multiple clock providers
and then adding clock driver for Exynos5260."

Acked-by: default avatarMike Turquette <mturquette@linaro.org>
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parents 34c453ce d39e55e0

Documentation/devicetree/bindings/clock/exynos5260-clock.txt

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* Samsung Exynos5260 Clock Controller



Exynos5260 has 13 clock controllers which are instantiated

independently from the device-tree. These clock controllers

generate and supply clocks to various hardware blocks within

the SoC.



Each clock is assigned an identifier and client nodes can use

this identifier to specify the clock which they consume. All

available clocks are defined as preprocessor macros in

dt-bindings/clock/exynos5260-clk.h header and can be used in

device tree sources.



External clocks:



There are several clocks that are generated outside the SoC. It

is expected that they are defined using standard clock bindings

with following clock-output-names:



 - "fin_pll" - PLL input clock from XXTI

 - "xrtcxti" - input clock from XRTCXTI

 - "ioclk_pcm_extclk" - pcm external operation clock

 - "ioclk_spdif_extclk" - spdif external operation clock

 - "ioclk_i2s_cdclk" - i2s0 codec clock



Phy clocks:



There are several clocks which are generated by specific PHYs.

These clocks are fed into the clock controller and then routed to

the hardware blocks. These clocks are defined as fixed clocks in the

driver with following names:



 - "phyclk_dptx_phy_ch3_txd_clk" - dp phy clock for channel 3

 - "phyclk_dptx_phy_ch2_txd_clk" - dp phy clock for channel 2

 - "phyclk_dptx_phy_ch1_txd_clk" - dp phy clock for channel 1

 - "phyclk_dptx_phy_ch0_txd_clk" - dp phy clock for channel 0

 - "phyclk_hdmi_phy_tmds_clko" - hdmi phy tmds clock

 - "phyclk_hdmi_phy_pixel_clko" - hdmi phy pixel clock

 - "phyclk_hdmi_link_o_tmds_clkhi" - hdmi phy for hdmi link

 - "phyclk_dptx_phy_o_ref_clk_24m" - dp phy reference clock

 - "phyclk_dptx_phy_clk_div2"

 - "phyclk_mipi_dphy_4l_m_rxclkesc0"

 - "phyclk_usbhost20_phy_phyclock" - usb 2.0 phy clock

 - "phyclk_usbhost20_phy_freeclk"

 - "phyclk_usbhost20_phy_clk48mohci"

 - "phyclk_usbdrd30_udrd30_pipe_pclk"

 - "phyclk_usbdrd30_udrd30_phyclock" - usb 3.0 phy clock



Required Properties for Clock Controller:



 - compatible: should be one of the following.

	1) "samsung,exynos5260-clock-top"

	2) "samsung,exynos5260-clock-peri"

	3) "samsung,exynos5260-clock-egl"

	4) "samsung,exynos5260-clock-kfc"

	5) "samsung,exynos5260-clock-g2d"

	6) "samsung,exynos5260-clock-mif"

	7) "samsung,exynos5260-clock-mfc"

	8) "samsung,exynos5260-clock-g3d"

	9) "samsung,exynos5260-clock-fsys"

	10) "samsung,exynos5260-clock-aud"

	11) "samsung,exynos5260-clock-isp"

	12) "samsung,exynos5260-clock-gscl"

	13) "samsung,exynos5260-clock-disp"



 - reg: physical base address of the controller and the length of

	memory mapped region.



 - #clock-cells: should be 1.



 - clocks: list of clock identifiers which are fed as the input to

	the given clock controller. Please refer the next section to find

	the input clocks for a given controller.



 - clock-names: list of names of clocks which are fed as the input

	to the given clock controller.



Input clocks for top clock controller:

	- fin_pll

	- dout_mem_pll

	- dout_bus_pll

	- dout_media_pll



Input clocks for peri clock controller:

	- fin_pll

	- ioclk_pcm_extclk

	- ioclk_i2s_cdclk

	- ioclk_spdif_extclk

	- phyclk_hdmi_phy_ref_cko

	- dout_aclk_peri_66

	- dout_sclk_peri_uart0

	- dout_sclk_peri_uart1

	- dout_sclk_peri_uart2

	- dout_sclk_peri_spi0_b

	- dout_sclk_peri_spi1_b

	- dout_sclk_peri_spi2_b

	- dout_aclk_peri_aud

	- dout_sclk_peri_spi0_b



Input clocks for egl clock controller:

	- fin_pll

	- dout_bus_pll



Input clocks for kfc clock controller:

	- fin_pll

	- dout_media_pll



Input clocks for g2d clock controller:

	- fin_pll

	- dout_aclk_g2d_333



Input clocks for mif clock controller:

	- fin_pll



Input clocks for mfc clock controller:

	- fin_pll

	- dout_aclk_mfc_333



Input clocks for g3d clock controller:

	- fin_pll



Input clocks for fsys clock controller:

	- fin_pll

	- phyclk_usbhost20_phy_phyclock

	- phyclk_usbhost20_phy_freeclk

	- phyclk_usbhost20_phy_clk48mohci

	- phyclk_usbdrd30_udrd30_pipe_pclk

	- phyclk_usbdrd30_udrd30_phyclock

	- dout_aclk_fsys_200



Input clocks for aud clock controller:

	- fin_pll

	- fout_aud_pll

	- ioclk_i2s_cdclk

	- ioclk_pcm_extclk



Input clocks for isp clock controller:

	- fin_pll

	- dout_aclk_isp1_266

	- dout_aclk_isp1_400

	- mout_aclk_isp1_266



Input clocks for gscl clock controller:

	- fin_pll

	- dout_aclk_gscl_400

	- dout_aclk_gscl_333



Input clocks for disp clock controller:

	- fin_pll

	- phyclk_dptx_phy_ch3_txd_clk

	- phyclk_dptx_phy_ch2_txd_clk

	- phyclk_dptx_phy_ch1_txd_clk

	- phyclk_dptx_phy_ch0_txd_clk

	- phyclk_hdmi_phy_tmds_clko

	- phyclk_hdmi_phy_ref_clko

	- phyclk_hdmi_phy_pixel_clko

	- phyclk_hdmi_link_o_tmds_clkhi

	- phyclk_mipi_dphy_4l_m_txbyte_clkhs

	- phyclk_dptx_phy_o_ref_clk_24m

	- phyclk_dptx_phy_clk_div2

	- phyclk_mipi_dphy_4l_m_rxclkesc0

	- phyclk_hdmi_phy_ref_cko

	- ioclk_spdif_extclk

	- dout_aclk_peri_aud

	- dout_aclk_disp_222

	- dout_sclk_disp_pixel

	- dout_aclk_disp_333



Example 1: An example of a clock controller node is listed below.



	clock_mfc: clock-controller@11090000 {

		compatible = "samsung,exynos5260-clock-mfc";

		clock = <&fin_pll>, <&clock_top TOP_DOUT_ACLK_MFC_333>;

		clock-names = "fin_pll", "dout_aclk_mfc_333";

		reg = <0x11090000 0x10000>;

		#clock-cells = <1>;

	};



Example 2: UART controller node that consumes the clock generated by the

		peri clock controller. Refer to the standard clock bindings for

		information about 'clocks' and 'clock-names' property.



	serial@12C00000 {

		compatible = "samsung,exynos4210-uart";

		reg = <0x12C00000 0x100>;

		interrupts = <0 146 0>;

		clocks = <&clock_peri PERI_PCLK_UART0>, <&clock_peri PERI_SCLK_UART0>;

		clock-names = "uart", "clk_uart_baud0";

	};

drivers/clk/samsung/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -5,6 +5,7 @@ 
obj-$(CONFIG_COMMON_CLK)	+= clk.o clk-pll.o

obj-$(CONFIG_ARCH_EXYNOS4)	+= clk-exynos4.o

obj-$(CONFIG_SOC_EXYNOS5250)	+= clk-exynos5250.o

obj-$(CONFIG_SOC_EXYNOS5260)	+= clk-exynos5260.o

obj-$(CONFIG_SOC_EXYNOS5420)	+= clk-exynos5420.o

obj-$(CONFIG_SOC_EXYNOS5440)	+= clk-exynos5440.o

obj-$(CONFIG_ARCH_EXYNOS)	+= clk-exynos-audss.o

drivers/clk/samsung/clk-exynos4.c

+25 −22
Original line number Diff line number Diff line
@@ -1043,7 +1043,7 @@ static unsigned long exynos4_get_xom(void) 
	return xom;

}



static void __init exynos4_clk_register_finpll(void)

static void __init exynos4_clk_register_finpll(struct samsung_clk_provider *ctx)

{

	struct samsung_fixed_rate_clock fclk;

	struct clk *clk;
@@ -1066,7 +1066,7 @@ static void __init exynos4_clk_register_finpll(void) 
	fclk.parent_name = NULL;

	fclk.flags = CLK_IS_ROOT;

	fclk.fixed_rate = finpll_f;

	samsung_clk_register_fixed_rate(&fclk, 1);

	samsung_clk_register_fixed_rate(ctx, &fclk, 1);



}
@@ -1176,22 +1176,25 @@ static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = { 
static void __init exynos4_clk_init(struct device_node *np,

				    enum exynos4_soc soc)

{

	struct samsung_clk_provider *ctx;

	exynos4_soc = soc;



	reg_base = of_iomap(np, 0);

	if (!reg_base)

		panic("%s: failed to map registers\n", __func__);



	samsung_clk_init(np, reg_base, CLK_NR_CLKS);

	ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);

	if (!ctx)

		panic("%s: unable to allocate context.\n", __func__);



	samsung_clk_of_register_fixed_ext(exynos4_fixed_rate_ext_clks,

	samsung_clk_of_register_fixed_ext(ctx, exynos4_fixed_rate_ext_clks,

			ARRAY_SIZE(exynos4_fixed_rate_ext_clks),

			ext_clk_match);



	exynos4_clk_register_finpll();

	exynos4_clk_register_finpll(ctx);



	if (exynos4_soc == EXYNOS4210) {

		samsung_clk_register_mux(exynos4210_mux_early,

		samsung_clk_register_mux(ctx, exynos4210_mux_early,

					ARRAY_SIZE(exynos4210_mux_early));



		if (_get_rate("fin_pll") == 24000000) {
@@ -1205,7 +1208,7 @@ static void __init exynos4_clk_init(struct device_node *np, 
			exynos4210_plls[vpll].rate_table =

							exynos4210_vpll_rates;



		samsung_clk_register_pll(exynos4210_plls,

		samsung_clk_register_pll(ctx, exynos4210_plls,

					ARRAY_SIZE(exynos4210_plls), reg_base);

	} else {

		if (_get_rate("fin_pll") == 24000000) {
@@ -1217,42 +1220,42 @@ static void __init exynos4_clk_init(struct device_node *np, 
							exynos4x12_vpll_rates;

		}



		samsung_clk_register_pll(exynos4x12_plls,

		samsung_clk_register_pll(ctx, exynos4x12_plls,

					ARRAY_SIZE(exynos4x12_plls), reg_base);

	}



	samsung_clk_register_fixed_rate(exynos4_fixed_rate_clks,

	samsung_clk_register_fixed_rate(ctx, exynos4_fixed_rate_clks,

			ARRAY_SIZE(exynos4_fixed_rate_clks));

	samsung_clk_register_mux(exynos4_mux_clks,

	samsung_clk_register_mux(ctx, exynos4_mux_clks,

			ARRAY_SIZE(exynos4_mux_clks));

	samsung_clk_register_div(exynos4_div_clks,

	samsung_clk_register_div(ctx, exynos4_div_clks,

			ARRAY_SIZE(exynos4_div_clks));

	samsung_clk_register_gate(exynos4_gate_clks,

	samsung_clk_register_gate(ctx, exynos4_gate_clks,

			ARRAY_SIZE(exynos4_gate_clks));



	if (exynos4_soc == EXYNOS4210) {

		samsung_clk_register_fixed_rate(exynos4210_fixed_rate_clks,

		samsung_clk_register_fixed_rate(ctx, exynos4210_fixed_rate_clks,

			ARRAY_SIZE(exynos4210_fixed_rate_clks));

		samsung_clk_register_mux(exynos4210_mux_clks,

		samsung_clk_register_mux(ctx, exynos4210_mux_clks,

			ARRAY_SIZE(exynos4210_mux_clks));

		samsung_clk_register_div(exynos4210_div_clks,

		samsung_clk_register_div(ctx, exynos4210_div_clks,

			ARRAY_SIZE(exynos4210_div_clks));

		samsung_clk_register_gate(exynos4210_gate_clks,

		samsung_clk_register_gate(ctx, exynos4210_gate_clks,

			ARRAY_SIZE(exynos4210_gate_clks));

		samsung_clk_register_alias(exynos4210_aliases,

		samsung_clk_register_alias(ctx, exynos4210_aliases,

			ARRAY_SIZE(exynos4210_aliases));

	} else {

		samsung_clk_register_mux(exynos4x12_mux_clks,

		samsung_clk_register_mux(ctx, exynos4x12_mux_clks,

			ARRAY_SIZE(exynos4x12_mux_clks));

		samsung_clk_register_div(exynos4x12_div_clks,

		samsung_clk_register_div(ctx, exynos4x12_div_clks,

			ARRAY_SIZE(exynos4x12_div_clks));

		samsung_clk_register_gate(exynos4x12_gate_clks,

		samsung_clk_register_gate(ctx, exynos4x12_gate_clks,

			ARRAY_SIZE(exynos4x12_gate_clks));

		samsung_clk_register_alias(exynos4x12_aliases,

		samsung_clk_register_alias(ctx, exynos4x12_aliases,

			ARRAY_SIZE(exynos4x12_aliases));

	}



	samsung_clk_register_alias(exynos4_aliases,

	samsung_clk_register_alias(ctx, exynos4_aliases,

			ARRAY_SIZE(exynos4_aliases));



	exynos4_clk_sleep_init();

drivers/clk/samsung/clk-exynos5250.c

+15 −10
Original line number Diff line number Diff line
@@ -686,6 +686,8 @@ static struct of_device_id ext_clk_match[] __initdata = { 
/* register exynox5250 clocks */

static void __init exynos5250_clk_init(struct device_node *np)

{

	struct samsung_clk_provider *ctx;



	if (np) {

		reg_base = of_iomap(np, 0);

		if (!reg_base)
@@ -694,11 +696,13 @@ static void __init exynos5250_clk_init(struct device_node *np) 
		panic("%s: unable to determine soc\n", __func__);

	}



	samsung_clk_init(np, reg_base, CLK_NR_CLKS);

	samsung_clk_of_register_fixed_ext(exynos5250_fixed_rate_ext_clks,

	ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);

	if (!ctx)

		panic("%s: unable to allocate context.\n", __func__);

	samsung_clk_of_register_fixed_ext(ctx, exynos5250_fixed_rate_ext_clks,

			ARRAY_SIZE(exynos5250_fixed_rate_ext_clks),

			ext_clk_match);

	samsung_clk_register_mux(exynos5250_pll_pmux_clks,

	samsung_clk_register_mux(ctx, exynos5250_pll_pmux_clks,

				ARRAY_SIZE(exynos5250_pll_pmux_clks));



	if (_get_rate("fin_pll") == 24 * MHZ) {
@@ -709,17 +713,18 @@ static void __init exynos5250_clk_init(struct device_node *np) 
	if (_get_rate("mout_vpllsrc") == 24 * MHZ)

		exynos5250_plls[vpll].rate_table =  vpll_24mhz_tbl;



	samsung_clk_register_pll(exynos5250_plls, ARRAY_SIZE(exynos5250_plls),

	samsung_clk_register_pll(ctx, exynos5250_plls,

			ARRAY_SIZE(exynos5250_plls),

			reg_base);

	samsung_clk_register_fixed_rate(exynos5250_fixed_rate_clks,

	samsung_clk_register_fixed_rate(ctx, exynos5250_fixed_rate_clks,

			ARRAY_SIZE(exynos5250_fixed_rate_clks));

	samsung_clk_register_fixed_factor(exynos5250_fixed_factor_clks,

	samsung_clk_register_fixed_factor(ctx, exynos5250_fixed_factor_clks,

			ARRAY_SIZE(exynos5250_fixed_factor_clks));

	samsung_clk_register_mux(exynos5250_mux_clks,

	samsung_clk_register_mux(ctx, exynos5250_mux_clks,

			ARRAY_SIZE(exynos5250_mux_clks));

	samsung_clk_register_div(exynos5250_div_clks,

	samsung_clk_register_div(ctx, exynos5250_div_clks,

			ARRAY_SIZE(exynos5250_div_clks));

	samsung_clk_register_gate(exynos5250_gate_clks,

	samsung_clk_register_gate(ctx, exynos5250_gate_clks,

			ARRAY_SIZE(exynos5250_gate_clks));



	exynos5250_clk_sleep_init();

drivers/clk/samsung/clk-exynos5260.c

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