Loading Documentation/devicetree/bindings/media/video/msm-cpp.txt +6 −0 Original line number Diff line number Diff line Loading @@ -60,6 +60,8 @@ Optional properties: - camss-vdd-supply: phandle to GDSC regulator controlling camss. - qcom,bus-master: Flag for presence of CPP bus master. It has to be set only for platforms that support such feature. - qcom,vbif-setting: The offset and value for vbif core qos registers. The first entry is register offset and second entry is register value. Example: Loading Loading @@ -97,6 +99,10 @@ Example: qcom,clock-rates = <0 0 0 0 465000000 0 0 465000000 0 0 0 0>; qcom,min-clock-rate = <320000000>; qcom,bus-master = <1>; qcom,vbif-qos-setting = <0x20 0x10000000>, <0x24 0x10000000>, <0x28 0x10000000>, <0x2C 0x10000000>; qcom,cpp-fw-payload-info { qcom,stripe-base = <553>; qcom,plane-base = <481>; Loading drivers/media/platform/msm/camera_v2/pproc/cpp/msm_cpp.c +40 −1 Original line number Diff line number Diff line Loading @@ -194,6 +194,7 @@ struct msm_cpp_timer_t { }; struct msm_cpp_timer_t cpp_timer; static void msm_cpp_set_vbif_reg_values(struct cpp_device *cpp_dev); static int msm_cpp_init_bandwidth_mgr(struct cpp_device *cpp_dev) { Loading Loading @@ -1114,7 +1115,7 @@ static int cpp_init_hardware(struct cpp_device *cpp_dev) rc = msm_cpp_update_gdscr_status(cpp_dev, true); if (rc < 0) { pr_err("update pcpp gdscr status failed\n"); pr_err("update cpp gdscr status failed\n"); goto req_irq_fail; } Loading Loading @@ -1158,6 +1159,7 @@ static int cpp_init_hardware(struct cpp_device *cpp_dev) MSM_CPP_MICRO_IRQGEN_CLR); } msm_cpp_set_vbif_reg_values(cpp_dev); return rc; pwr_collapse_reset: Loading Loading @@ -3712,6 +3714,43 @@ static int msm_cpp_update_gdscr_status(struct cpp_device *cpp_dev, end: return rc; } static void msm_cpp_set_vbif_reg_values(struct cpp_device *cpp_dev) { int i, reg, val; const u32 *vbif_qos_arr = NULL; int vbif_qos_len = 0; struct platform_device *pdev; pr_debug("%s\n", __func__); if (cpp_dev != NULL) { pdev = cpp_dev->pdev; vbif_qos_arr = of_get_property(pdev->dev.of_node, "qcom,vbif-qos-setting", &vbif_qos_len); if (!vbif_qos_arr || (vbif_qos_len & 1)) { pr_debug("%s: vbif qos setting not found\n", __func__); vbif_qos_len = 0; } vbif_qos_len /= sizeof(u32); pr_debug("%s: vbif_qos_len %d\n", __func__, vbif_qos_len); if (cpp_dev->vbif_base) { for (i = 0; i < vbif_qos_len; i = i+2) { reg = be32_to_cpu(vbif_qos_arr[i]); val = be32_to_cpu(vbif_qos_arr[i+1]); pr_debug("%s: DT: offset %x, val %x\n", __func__, reg, val); pr_debug("%s: before write to register 0x%x\n", __func__, msm_camera_io_r( cpp_dev->vbif_base + reg)); msm_camera_io_w(val, cpp_dev->vbif_base + reg); pr_debug("%s: after write to register 0x%x\n", __func__, msm_camera_io_r( cpp_dev->vbif_base + reg)); } } } } static int cpp_probe(struct platform_device *pdev) { Loading Loading
Documentation/devicetree/bindings/media/video/msm-cpp.txt +6 −0 Original line number Diff line number Diff line Loading @@ -60,6 +60,8 @@ Optional properties: - camss-vdd-supply: phandle to GDSC regulator controlling camss. - qcom,bus-master: Flag for presence of CPP bus master. It has to be set only for platforms that support such feature. - qcom,vbif-setting: The offset and value for vbif core qos registers. The first entry is register offset and second entry is register value. Example: Loading Loading @@ -97,6 +99,10 @@ Example: qcom,clock-rates = <0 0 0 0 465000000 0 0 465000000 0 0 0 0>; qcom,min-clock-rate = <320000000>; qcom,bus-master = <1>; qcom,vbif-qos-setting = <0x20 0x10000000>, <0x24 0x10000000>, <0x28 0x10000000>, <0x2C 0x10000000>; qcom,cpp-fw-payload-info { qcom,stripe-base = <553>; qcom,plane-base = <481>; Loading
drivers/media/platform/msm/camera_v2/pproc/cpp/msm_cpp.c +40 −1 Original line number Diff line number Diff line Loading @@ -194,6 +194,7 @@ struct msm_cpp_timer_t { }; struct msm_cpp_timer_t cpp_timer; static void msm_cpp_set_vbif_reg_values(struct cpp_device *cpp_dev); static int msm_cpp_init_bandwidth_mgr(struct cpp_device *cpp_dev) { Loading Loading @@ -1114,7 +1115,7 @@ static int cpp_init_hardware(struct cpp_device *cpp_dev) rc = msm_cpp_update_gdscr_status(cpp_dev, true); if (rc < 0) { pr_err("update pcpp gdscr status failed\n"); pr_err("update cpp gdscr status failed\n"); goto req_irq_fail; } Loading Loading @@ -1158,6 +1159,7 @@ static int cpp_init_hardware(struct cpp_device *cpp_dev) MSM_CPP_MICRO_IRQGEN_CLR); } msm_cpp_set_vbif_reg_values(cpp_dev); return rc; pwr_collapse_reset: Loading Loading @@ -3712,6 +3714,43 @@ static int msm_cpp_update_gdscr_status(struct cpp_device *cpp_dev, end: return rc; } static void msm_cpp_set_vbif_reg_values(struct cpp_device *cpp_dev) { int i, reg, val; const u32 *vbif_qos_arr = NULL; int vbif_qos_len = 0; struct platform_device *pdev; pr_debug("%s\n", __func__); if (cpp_dev != NULL) { pdev = cpp_dev->pdev; vbif_qos_arr = of_get_property(pdev->dev.of_node, "qcom,vbif-qos-setting", &vbif_qos_len); if (!vbif_qos_arr || (vbif_qos_len & 1)) { pr_debug("%s: vbif qos setting not found\n", __func__); vbif_qos_len = 0; } vbif_qos_len /= sizeof(u32); pr_debug("%s: vbif_qos_len %d\n", __func__, vbif_qos_len); if (cpp_dev->vbif_base) { for (i = 0; i < vbif_qos_len; i = i+2) { reg = be32_to_cpu(vbif_qos_arr[i]); val = be32_to_cpu(vbif_qos_arr[i+1]); pr_debug("%s: DT: offset %x, val %x\n", __func__, reg, val); pr_debug("%s: before write to register 0x%x\n", __func__, msm_camera_io_r( cpp_dev->vbif_base + reg)); msm_camera_io_w(val, cpp_dev->vbif_base + reg); pr_debug("%s: after write to register 0x%x\n", __func__, msm_camera_io_r( cpp_dev->vbif_base + reg)); } } } } static int cpp_probe(struct platform_device *pdev) { Loading