Loading arch/arm/boot/dts/qcom/mdmcalifornium-usb.dtsi +1 −0 Original line number Diff line number Diff line Loading @@ -54,6 +54,7 @@ clock-names = "core_clk", "iface_clk", "utmi_clk", "sleep_clk", "xo", "cfg_ahb_clk"; qcom,core-clk-rate = <120000000>; dwc3@8a00000 { compatible = "snps,dwc3"; reg = <0x08a00000 0xcd00>; Loading arch/arm/boot/dts/qcom/msm8996.dtsi +2 −0 Original line number Diff line number Diff line Loading @@ -1896,6 +1896,7 @@ clock-names = "core_clk", "iface_clk", "bus_aggr_clk", "utmi_clk", "sleep_clk", "xo", "cfg_ahb_clk"; qcom,core-clk-rate = <120000000>; dwc3@6a00000 { compatible = "snps,dwc3"; reg = <0x06a00000 0xc8d0>; Loading Loading @@ -2002,6 +2003,7 @@ clock-names = "core_clk", "iface_clk", "utmi_clk", "sleep_clk", "xo", "cfg_ahb_clk"; qcom,core-clk-rate = <60000000>; dwc3@7600000 { compatible = "snps,dwc3"; reg = <0x07600000 0xc8d0>; Loading Loading
arch/arm/boot/dts/qcom/mdmcalifornium-usb.dtsi +1 −0 Original line number Diff line number Diff line Loading @@ -54,6 +54,7 @@ clock-names = "core_clk", "iface_clk", "utmi_clk", "sleep_clk", "xo", "cfg_ahb_clk"; qcom,core-clk-rate = <120000000>; dwc3@8a00000 { compatible = "snps,dwc3"; reg = <0x08a00000 0xcd00>; Loading
arch/arm/boot/dts/qcom/msm8996.dtsi +2 −0 Original line number Diff line number Diff line Loading @@ -1896,6 +1896,7 @@ clock-names = "core_clk", "iface_clk", "bus_aggr_clk", "utmi_clk", "sleep_clk", "xo", "cfg_ahb_clk"; qcom,core-clk-rate = <120000000>; dwc3@6a00000 { compatible = "snps,dwc3"; reg = <0x06a00000 0xc8d0>; Loading Loading @@ -2002,6 +2003,7 @@ clock-names = "core_clk", "iface_clk", "utmi_clk", "sleep_clk", "xo", "cfg_ahb_clk"; qcom,core-clk-rate = <60000000>; dwc3@7600000 { compatible = "snps,dwc3"; reg = <0x07600000 0xc8d0>; Loading