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Commit 69f7876b authored by Dave Airlie's avatar Dave Airlie
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Merge remote branch 'keithp/drm-intel-next' of /ssd/git/drm-next into drm-core-next

* 'keithp/drm-intel-next' of /ssd/git/drm-next: (301 commits)
  drm/i915: split PCH clock gating init
  drm/i915: add Ivybridge clock gating init function
  drm/i915: Update the location of the ringbuffers' HWS_PGA registers for IVB.
  drm/i915: Add support for fence registers on Ivybridge.
  drm/i915: Use existing function instead of open-coding fence reg clear.
  drm/i915: split clock gating init into per-chipset functions
  drm/i915: set IBX pch type explicitly
  drm/i915: add Ivy Bridge PCI IDs and driver feature structs
  drm/i915: add PantherPoint PCH ID
  agp/intel: add Ivy Bridge support
  drm/i915: ring support for Ivy Bridge
  drm/i915: page flip support for Ivy Bridge
  drm/i915: interrupt & vblank support for Ivy Bridge
  drm/i915: treat Ivy Bridge watermarks like Sandy Bridge
  drm/i915: manual FDI training for Ivy Bridge
  drm/i915: add swizzle/tiling support for Ivy Bridge
  drm/i915: Ivy Bridge has split display and pipe control
  drm/i915: add IS_IVYBRIDGE macro for checks
  drm/i915: add IS_GEN7 macro to cover Ivy Bridge and later
  drm/i915: split enable/disable vblank code into chipset specific functions
  ...
parents 0eacdba3 645c62a5
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+1 −0
Original line number Diff line number Diff line
@@ -294,6 +294,7 @@
<!ENTITY sub-srggb10 SYSTEM "v4l/pixfmt-srggb10.xml">
<!ENTITY sub-srggb8 SYSTEM "v4l/pixfmt-srggb8.xml">
<!ENTITY sub-y10 SYSTEM "v4l/pixfmt-y10.xml">
<!ENTITY sub-y12 SYSTEM "v4l/pixfmt-y12.xml">
<!ENTITY sub-pixfmt SYSTEM "v4l/pixfmt.xml">
<!ENTITY sub-cropcap SYSTEM "v4l/vidioc-cropcap.xml">
<!ENTITY sub-dbg-g-register SYSTEM "v4l/vidioc-dbg-g-register.xml">
+1 −1
Original line number Diff line number Diff line
@@ -34,7 +34,7 @@
      <varlistentry>
	<term><parameter>request</parameter></term>
	<listitem>
	  <para>MEDIA_IOC_ENUM_LINKS</para>
	  <para>MEDIA_IOC_SETUP_LINK</para>
	</listitem>
      </varlistentry>
      <varlistentry>
+79 −0
Original line number Diff line number Diff line
<refentry id="V4L2-PIX-FMT-Y12">
  <refmeta>
    <refentrytitle>V4L2_PIX_FMT_Y12 ('Y12 ')</refentrytitle>
    &manvol;
  </refmeta>
  <refnamediv>
    <refname><constant>V4L2_PIX_FMT_Y12</constant></refname>
    <refpurpose>Grey-scale image</refpurpose>
  </refnamediv>
  <refsect1>
    <title>Description</title>

    <para>This is a grey-scale image with a depth of 12 bits per pixel. Pixels
are stored in 16-bit words with unused high bits padded with 0. The least
significant byte is stored at lower memory addresses (little-endian).</para>

    <example>
      <title><constant>V4L2_PIX_FMT_Y12</constant> 4 &times; 4
pixel image</title>

      <formalpara>
	<title>Byte Order.</title>
	<para>Each cell is one byte.
	  <informaltable frame="none">
	    <tgroup cols="9" align="center">
	      <colspec align="left" colwidth="2*" />
	      <tbody valign="top">
		<row>
		  <entry>start&nbsp;+&nbsp;0:</entry>
		  <entry>Y'<subscript>00low</subscript></entry>
		  <entry>Y'<subscript>00high</subscript></entry>
		  <entry>Y'<subscript>01low</subscript></entry>
		  <entry>Y'<subscript>01high</subscript></entry>
		  <entry>Y'<subscript>02low</subscript></entry>
		  <entry>Y'<subscript>02high</subscript></entry>
		  <entry>Y'<subscript>03low</subscript></entry>
		  <entry>Y'<subscript>03high</subscript></entry>
		</row>
		<row>
		  <entry>start&nbsp;+&nbsp;8:</entry>
		  <entry>Y'<subscript>10low</subscript></entry>
		  <entry>Y'<subscript>10high</subscript></entry>
		  <entry>Y'<subscript>11low</subscript></entry>
		  <entry>Y'<subscript>11high</subscript></entry>
		  <entry>Y'<subscript>12low</subscript></entry>
		  <entry>Y'<subscript>12high</subscript></entry>
		  <entry>Y'<subscript>13low</subscript></entry>
		  <entry>Y'<subscript>13high</subscript></entry>
		</row>
		<row>
		  <entry>start&nbsp;+&nbsp;16:</entry>
		  <entry>Y'<subscript>20low</subscript></entry>
		  <entry>Y'<subscript>20high</subscript></entry>
		  <entry>Y'<subscript>21low</subscript></entry>
		  <entry>Y'<subscript>21high</subscript></entry>
		  <entry>Y'<subscript>22low</subscript></entry>
		  <entry>Y'<subscript>22high</subscript></entry>
		  <entry>Y'<subscript>23low</subscript></entry>
		  <entry>Y'<subscript>23high</subscript></entry>
		</row>
		<row>
		  <entry>start&nbsp;+&nbsp;24:</entry>
		  <entry>Y'<subscript>30low</subscript></entry>
		  <entry>Y'<subscript>30high</subscript></entry>
		  <entry>Y'<subscript>31low</subscript></entry>
		  <entry>Y'<subscript>31high</subscript></entry>
		  <entry>Y'<subscript>32low</subscript></entry>
		  <entry>Y'<subscript>32high</subscript></entry>
		  <entry>Y'<subscript>33low</subscript></entry>
		  <entry>Y'<subscript>33high</subscript></entry>
		</row>
	      </tbody>
	    </tgroup>
	  </informaltable>
	</para>
      </formalpara>
    </example>
  </refsect1>
</refentry>
+1 −0
Original line number Diff line number Diff line
@@ -696,6 +696,7 @@ information.</para>
    &sub-packed-yuv;
    &sub-grey;
    &sub-y10;
    &sub-y12;
    &sub-y16;
    &sub-yuyv;
    &sub-uyvy;
+59 −0
Original line number Diff line number Diff line
@@ -456,6 +456,23 @@
	      <entry>b<subscript>1</subscript></entry>
	      <entry>b<subscript>0</subscript></entry>
	    </row>
	    <row id="V4L2-MBUS-FMT-SGBRG8-1X8">
	      <entry>V4L2_MBUS_FMT_SGBRG8_1X8</entry>
	      <entry>0x3013</entry>
	      <entry></entry>
	      <entry>-</entry>
	      <entry>-</entry>
	      <entry>-</entry>
	      <entry>-</entry>
	      <entry>g<subscript>7</subscript></entry>
	      <entry>g<subscript>6</subscript></entry>
	      <entry>g<subscript>5</subscript></entry>
	      <entry>g<subscript>4</subscript></entry>
	      <entry>g<subscript>3</subscript></entry>
	      <entry>g<subscript>2</subscript></entry>
	      <entry>g<subscript>1</subscript></entry>
	      <entry>g<subscript>0</subscript></entry>
	    </row>
	    <row id="V4L2-MBUS-FMT-SGRBG8-1X8">
	      <entry>V4L2_MBUS_FMT_SGRBG8_1X8</entry>
	      <entry>0x3002</entry>
@@ -473,6 +490,23 @@
	      <entry>g<subscript>1</subscript></entry>
	      <entry>g<subscript>0</subscript></entry>
	    </row>
	    <row id="V4L2-MBUS-FMT-SRGGB8-1X8">
	      <entry>V4L2_MBUS_FMT_SRGGB8_1X8</entry>
	      <entry>0x3014</entry>
	      <entry></entry>
	      <entry>-</entry>
	      <entry>-</entry>
	      <entry>-</entry>
	      <entry>-</entry>
	      <entry>r<subscript>7</subscript></entry>
	      <entry>r<subscript>6</subscript></entry>
	      <entry>r<subscript>5</subscript></entry>
	      <entry>r<subscript>4</subscript></entry>
	      <entry>r<subscript>3</subscript></entry>
	      <entry>r<subscript>2</subscript></entry>
	      <entry>r<subscript>1</subscript></entry>
	      <entry>r<subscript>0</subscript></entry>
	    </row>
	    <row id="V4L2-MBUS-FMT-SBGGR10-DPCM8-1X8">
	      <entry>V4L2_MBUS_FMT_SBGGR10_DPCM8_1X8</entry>
	      <entry>0x300b</entry>
@@ -2159,6 +2193,31 @@
	      <entry>u<subscript>1</subscript></entry>
	      <entry>u<subscript>0</subscript></entry>
	    </row>
	    <row id="V4L2-MBUS-FMT-Y12-1X12">
	      <entry>V4L2_MBUS_FMT_Y12_1X12</entry>
	      <entry>0x2013</entry>
	      <entry></entry>
	      <entry>-</entry>
	      <entry>-</entry>
	      <entry>-</entry>
	      <entry>-</entry>
	      <entry>-</entry>
	      <entry>-</entry>
	      <entry>-</entry>
	      <entry>-</entry>
	      <entry>y<subscript>11</subscript></entry>
	      <entry>y<subscript>10</subscript></entry>
	      <entry>y<subscript>9</subscript></entry>
	      <entry>y<subscript>8</subscript></entry>
	      <entry>y<subscript>7</subscript></entry>
	      <entry>y<subscript>6</subscript></entry>
	      <entry>y<subscript>5</subscript></entry>
	      <entry>y<subscript>4</subscript></entry>
	      <entry>y<subscript>3</subscript></entry>
	      <entry>y<subscript>2</subscript></entry>
	      <entry>y<subscript>1</subscript></entry>
	      <entry>y<subscript>0</subscript></entry>
	    </row>
	    <row id="V4L2-MBUS-FMT-UYVY8-1X16">
	      <entry>V4L2_MBUS_FMT_UYVY8_1X16</entry>
	      <entry>0x200f</entry>
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