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Commit 645c62a5 authored by Jesse Barnes's avatar Jesse Barnes Committed by Keith Packard
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drm/i915: split PCH clock gating init 



Ibex Peak and CougarPoint already require a different setting (added
here), and future chips will likely follow that precedent.

Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: default avatarKeith Packard <keithp@keithp.com>
Signed-off-by: default avatarKeith Packard <keithp@keithp.com>
parent 28963a3e

drivers/gpu/drm/i915/i915_drv.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -210,6 +210,7 @@ struct drm_i915_display_funcs { 
			     struct drm_framebuffer *old_fb);

			     struct drm_framebuffer *old_fb);

	void (*fdi_link_train)(struct drm_crtc *crtc);

	void (*fdi_link_train)(struct drm_crtc *crtc);

	void (*init_clock_gating)(struct drm_device *dev);

	void (*init_clock_gating)(struct drm_device *dev);

	void (*init_pch_clock_gating)(struct drm_device *dev);

	/* clock updates for mode set */

	/* clock updates for mode set */

	/* cursor updates */

	/* cursor updates */

	/* render clock increase/decrease */

	/* render clock increase/decrease */

drivers/gpu/drm/i915/i915_reg.h

+3 −0
Original line number Original line Diff line number Diff line
@@ -3074,6 +3074,9 @@ 
#define  TRANS_6BPC             (2<<5)

#define  TRANS_6BPC             (2<<5)

#define  TRANS_12BPC            (3<<5)

#define  TRANS_12BPC            (3<<5)





#define SOUTH_CHICKEN2		0xc2004

#define  DPLS_EDP_PPS_FIX_DIS	(1<<0)



#define _FDI_RXA_CHICKEN         0xc200c

#define _FDI_RXA_CHICKEN         0xc200c

#define _FDI_RXB_CHICKEN         0xc2010

#define _FDI_RXB_CHICKEN         0xc2010

#define  FDI_RX_PHASE_SYNC_POINTER_OVR	(1<<1)

#define  FDI_RX_PHASE_SYNC_POINTER_OVR	(1<<1)

drivers/gpu/drm/i915/i915_suspend.c

+1 −2
Original line number Original line Diff line number Diff line
@@ -863,8 +863,7 @@ int i915_restore_state(struct drm_device *dev) 
		I915_WRITE(IMR, dev_priv->saveIMR);

		I915_WRITE(IMR, dev_priv->saveIMR);

	}

	}





	/* Clock gating state */

	intel_init_clock_gating(dev);

	dev_priv->display.init_clock_gating(dev);





	if (IS_IRONLAKE_M(dev)) {

	if (IS_IRONLAKE_M(dev)) {

		ironlake_enable_drps(dev);

		ironlake_enable_drps(dev);

drivers/gpu/drm/i915/intel_display.c

+41 −22
Original line number Original line Diff line number Diff line
@@ -7231,13 +7231,6 @@ static void ironlake_init_clock_gating(struct drm_device *dev) 




	I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);

	I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);





	/*

	 * On Ibex Peak and Cougar Point, we need to disable clock

	 * gating for the panel power sequencer or it will fail to

	 * start up when no ports are active.

	 */

	I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);



	/*

	/*

	 * According to the spec the following bits should be set in

	 * According to the spec the following bits should be set in

	 * order to enable memory self-refresh

	 * order to enable memory self-refresh
@@ -7295,13 +7288,6 @@ static void gen6_init_clock_gating(struct drm_device *dev) 




	I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);

	I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);





	/*

	 * On Ibex Peak and Cougar Point, we need to disable clock

	 * gating for the panel power sequencer or it will fail to

	 * start up when no ports are active.

	 */

	I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);



	I915_WRITE(ILK_DISPLAY_CHICKEN2,

	I915_WRITE(ILK_DISPLAY_CHICKEN2,

		   I915_READ(ILK_DISPLAY_CHICKEN2) |

		   I915_READ(ILK_DISPLAY_CHICKEN2) |

		   ILK_ELPIN_409_SELECT);

		   ILK_ELPIN_409_SELECT);
@@ -7344,13 +7330,6 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) 




	I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);

	I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);





	/*

	 * On Ibex Peak and Cougar Point, we need to disable clock

	 * gating for the panel power sequencer or it will fail to

	 * start up when no ports are active.

	 */

	I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);



	I915_WRITE(WM3_LP_ILK, 0);

	I915_WRITE(WM3_LP_ILK, 0);

	I915_WRITE(WM2_LP_ILK, 0);

	I915_WRITE(WM2_LP_ILK, 0);

	I915_WRITE(WM1_LP_ILK, 0);

	I915_WRITE(WM1_LP_ILK, 0);
@@ -7428,6 +7407,32 @@ static void i830_init_clock_gating(struct drm_device *dev) 
	I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);

	I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);

}

}





static void ibx_init_clock_gating(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;



	/*

	 * On Ibex Peak and Cougar Point, we need to disable clock

	 * gating for the panel power sequencer or it will fail to

	 * start up when no ports are active.

	 */

	I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);

}



static void cpt_init_clock_gating(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;



	/*

	 * On Ibex Peak and Cougar Point, we need to disable clock

	 * gating for the panel power sequencer or it will fail to

	 * start up when no ports are active.

	 */

	I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);

	I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |

		   DPLS_EDP_PPS_FIX_DIS);

}



static void ironlake_teardown_rc6(struct drm_device *dev)

static void ironlake_teardown_rc6(struct drm_device *dev)

{

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -7543,6 +7548,15 @@ void ironlake_enable_rc6(struct drm_device *dev) 
	mutex_unlock(&dev->struct_mutex);

	mutex_unlock(&dev->struct_mutex);

}

}





void intel_init_clock_gating(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;



	dev_priv->display.init_clock_gating(dev);



	if (dev_priv->display.init_pch_clock_gating)

		dev_priv->display.init_pch_clock_gating(dev);

}





/* Set up chip specific display functions */

/* Set up chip specific display functions */

static void intel_init_display(struct drm_device *dev)

static void intel_init_display(struct drm_device *dev)
@@ -7600,6 +7614,11 @@ static void intel_init_display(struct drm_device *dev) 




	/* For FIFO watermark updates */

	/* For FIFO watermark updates */

	if (HAS_PCH_SPLIT(dev)) {

	if (HAS_PCH_SPLIT(dev)) {

		if (HAS_PCH_IBX(dev))

			dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;

		else if (HAS_PCH_CPT(dev))

			dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;



		if (IS_GEN5(dev)) {

		if (IS_GEN5(dev)) {

			if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)

			if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)

				dev_priv->display.update_wm = ironlake_update_wm;

				dev_priv->display.update_wm = ironlake_update_wm;
@@ -7802,7 +7821,7 @@ void intel_modeset_init(struct drm_device *dev) 
	i915_disable_vga(dev);

	i915_disable_vga(dev);

	intel_setup_outputs(dev);

	intel_setup_outputs(dev);





	dev_priv->display.init_clock_gating(dev);

	intel_init_clock_gating(dev);





	if (IS_IRONLAKE_M(dev)) {

	if (IS_IRONLAKE_M(dev)) {

		ironlake_enable_drps(dev);

		ironlake_enable_drps(dev);

drivers/gpu/drm/i915/intel_drv.h

+2 −0
Original line number Original line Diff line number Diff line
@@ -344,4 +344,6 @@ extern int intel_overlay_attrs(struct drm_device *dev, void *data, 




extern void intel_fb_output_poll_changed(struct drm_device *dev);

extern void intel_fb_output_poll_changed(struct drm_device *dev);

extern void intel_fb_restore_mode(struct drm_device *dev);

extern void intel_fb_restore_mode(struct drm_device *dev);



extern void intel_init_clock_gating(struct drm_device *dev);

#endif /* __INTEL_DRV_H__ */
 
#endif /* __INTEL_DRV_H__ */