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Commit 28963a3e authored by Jesse Barnes's avatar Jesse Barnes Committed by Keith Packard
Browse files

drm/i915: add Ivybridge clock gating init function 



Some of the bits have changed, including one we were setting that enables
a VGA test mode, preventing pipe B from working at all.  So add a new
IVB specific function with the right bits.

Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: default avatarKeith Packard <keithp@keithp.com>
Signed-off-by: default avatarKeith Packard <keithp@keithp.com>
parent 4593010b

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -2825,6 +2825,7 @@ 
#define  ILK_eDP_A_DISABLE		(1<<24)

#define  ILK_DESKTOP			(1<<23)

#define ILK_DSPCLK_GATE		0x42020

#define  IVB_VRHUNIT_CLK_GATE	(1<<28)

#define  ILK_DPARB_CLK_GATE	(1<<5)

#define  ILK_DPFD_CLK_GATE	(1<<7)

drivers/gpu/drm/i915/intel_display.c

+28 −1
Original line number Diff line number Diff line
@@ -7336,6 +7336,33 @@ static void gen6_init_clock_gating(struct drm_device *dev) 
			   DISPPLANE_TRICKLE_FEED_DISABLE);

}



static void ivybridge_init_clock_gating(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	int pipe;

	uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;



	I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);



	/*

	 * On Ibex Peak and Cougar Point, we need to disable clock

	 * gating for the panel power sequencer or it will fail to

	 * start up when no ports are active.

	 */

	I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);



	I915_WRITE(WM3_LP_ILK, 0);

	I915_WRITE(WM2_LP_ILK, 0);

	I915_WRITE(WM1_LP_ILK, 0);



	I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);



	for_each_pipe(pipe)

		I915_WRITE(DSPCNTR(pipe),

			   I915_READ(DSPCNTR(pipe)) |

			   DISPPLANE_TRICKLE_FEED_DISABLE);

}



static void g4x_init_clock_gating(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -7603,7 +7630,7 @@ static void intel_init_display(struct drm_device *dev) 
					      "Disable CxSR\n");

				dev_priv->display.update_wm = NULL;

			}

			dev_priv->display.init_clock_gating = gen6_init_clock_gating;

			dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;



		} else

			dev_priv->display.update_wm = NULL;