Merge "ARM: dts: msm: Remove ICE specific configurations for msm8996" (6198cbc6) · Commits · e / devices / android_kernel_xiaomi_markw

arch/arm/boot/dts/qcom/msm8996.dtsi

+37 −20

Original line number	Original line	Diff line number	Diff line
	@@ -1176,10 +1176,29 @@
	interrupt-names = "ufs_ice_nonsec_level_irq", "ufs_ice_sec_level_irq";		interrupt-names = "ufs_ice_nonsec_level_irq", "ufs_ice_sec_level_irq";
	interrupts = <0 258 0>, <0 257 0>;		interrupts = <0 258 0>, <0 257 0>;
	qcom,enable-ice-clk;		qcom,enable-ice-clk;
	clock-names = "ice_core_clk_src", "ice_core_clk";		clock-names = "ufs_core_clk_src",
	clocks = <&clock_gcc clk_ufs_ice_core_clk_src>,		"ufs_core_clk",
			"bus_clk",
			"iface_clk",
			"ice_core_clk_src",
			"ice_core_clk";
			clocks = <&clock_gcc clk_ufs_axi_clk_src>,
			<&clock_gcc clk_gcc_ufs_axi_clk>,
			<&clock_gcc clk_gcc_sys_noc_ufs_axi_clk>,
			<&clock_gcc clk_gcc_ufs_ahb_clk>,
			<&clock_gcc clk_ufs_ice_core_clk_src>,
	<&clock_gcc clk_gcc_ufs_ice_core_clk>;		<&clock_gcc clk_gcc_ufs_ice_core_clk>;
	qcom,op-freq-hz = <300000000>, <0>;		qcom,op-freq-hz = <0>, <0>, <0>,<0>,
			<300000000>, <0>;
			vdd-hba-supply = <&gdsc_ufs>;
			qcom,msm-bus,name = "ufs_ice_noc";
			qcom,msm-bus,num-cases = <2>;
			qcom,msm-bus,num-paths = <1>;
			qcom,msm-bus,vectors-KBps =
			<1 650 0 0>, /* No vote */
			<1 650 1000 0>; /* Max. bandwidth */
			qcom,bus-vector-names = "MIN",
			"MAX";
	qcom,instance-type = "ufs";		qcom,instance-type = "ufs";
	status = "disabled";		status = "disabled";
	};		};
	@@ -1190,10 +1209,21 @@
	interrupt-names = "sdcc_ice_nonsec_level_irq", "sdcc_ice_sec_level_irq";		interrupt-names = "sdcc_ice_nonsec_level_irq", "sdcc_ice_sec_level_irq";
	interrupts = <0 461 0>, <0 460 0>;		interrupts = <0 461 0>, <0 460 0>;
	qcom,enable-ice-clk;		qcom,enable-ice-clk;
	clock-names = "ice_core_clk_src", "ice_core_clk";		clock-names = "ice_core_clk_src", "ice_core_clk",
			"bus_clk", "iface_clk";
	clocks = <&clock_gcc clk_sdcc1_ice_core_clk_src>,		clocks = <&clock_gcc clk_sdcc1_ice_core_clk_src>,
	<&clock_gcc clk_gcc_sdcc1_ice_core_clk>;		<&clock_gcc clk_gcc_sdcc1_ice_core_clk>,
			<&clock_gcc clk_gcc_sdcc1_apps_clk>,
			<&clock_gcc clk_gcc_sdcc1_ahb_clk>;
	qcom,op-freq-hz = <300000000>, <0>;		qcom,op-freq-hz = <300000000>, <0>;
			qcom,msm-bus,name = "sdcc_ice_noc";
			qcom,msm-bus,num-cases = <2>;
			qcom,msm-bus,num-paths = <1>;
			qcom,msm-bus,vectors-KBps =
			<78 512 0 0>, /* No vote */
			<78 512 1000 0>; /* Max. bandwidth */
			qcom,bus-vector-names = "MIN",
			"MAX";
	qcom,instance-type = "sdcc";		qcom,instance-type = "sdcc";
	status = "disabled";		status = "disabled";
	};		};
	@@ -2580,25 +2610,12 @@
	<55 512 120000 1200000>,		<55 512 120000 1200000>,
	<55 512 393600 3936000>;		<55 512 393600 3936000>;
	clock-names = "core_clk_src", "core_clk",		clock-names = "core_clk_src", "core_clk",
	"iface_clk", "bus_clk",		"iface_clk", "bus_clk";
	"ufs_core_clk_src", "ufs_core_clk",
	"ufs_bus_clk", "ufs_iface_clk",
	"sdcc_core_clk_src", "sdcc_core_clk",
	"sdcc_bus_clk", "sdcc_iface_clk";
	clocks = <&clock_gcc clk_ce1_clk>,		clocks = <&clock_gcc clk_ce1_clk>,
	<&clock_gcc clk_qseecom_ce1_clk>,		<&clock_gcc clk_qseecom_ce1_clk>,
	<&clock_gcc clk_gcc_ce1_ahb_m_clk>,		<&clock_gcc clk_gcc_ce1_ahb_m_clk>,
	<&clock_gcc clk_gcc_ce1_axi_m_clk>,		<&clock_gcc clk_gcc_ce1_axi_m_clk>;
	<&clock_gcc clk_ufs_ice_core_clk_src>,
	<&clock_gcc clk_gcc_ufs_ice_core_clk>,
	<&clock_gcc clk_gcc_sys_noc_ufs_axi_clk>,
	<&clock_gcc clk_gcc_ufs_ahb_clk>,
	<&clock_gcc clk_sdcc1_ice_core_clk_src>,
	<&clock_gcc clk_gcc_sdcc1_ice_core_clk>,
	<&clock_gcc clk_gcc_sdcc1_ahb_clk>,
	<&clock_gcc clk_gcc_sdcc1_apps_clk>;
	qcom,ce-opp-freq = <171430000>;		qcom,ce-opp-freq = <171430000>;
	vdd-hba-supply = <&gdsc_ufs>;
	};		};

	qcom,sensor-information {		qcom,sensor-information {

drivers/misc/qseecom.c

+14 −121

Original line number	Original line	Diff line number	Diff line
	@@ -45,6 +45,7 @@
	#include <asm/cacheflush.h>		#include <asm/cacheflush.h>
	#include "qseecom_legacy.h"		#include "qseecom_legacy.h"
	#include "qseecom_kernel.h"		#include "qseecom_kernel.h"
			#include <crypto/ice.h>

	#ifdef CONFIG_COMPAT		#ifdef CONFIG_COMPAT
	#include <linux/compat.h>		#include <linux/compat.h>
	@@ -107,8 +108,6 @@ enum qseecom_client_handle_type {
	enum qseecom_ce_hw_instance {		enum qseecom_ce_hw_instance {
	CLK_QSEE = 0,		CLK_QSEE = 0,
	CLK_CE_DRV,		CLK_CE_DRV,
	CLK_UFS_ICE,
	CLK_SDCC_ICE,
	CLK_INVALID,		CLK_INVALID,
	};		};

	@@ -190,9 +189,6 @@ struct qseecom_control {
	uint32_t qsee_perf_client;		uint32_t qsee_perf_client;
	struct qseecom_clk qsee;		struct qseecom_clk qsee;
	struct qseecom_clk ce_drv;		struct qseecom_clk ce_drv;
	struct qseecom_clk ce_ice;
	struct regulator *reg;
	bool is_regulator_available;

	bool support_bus_scaling;		bool support_bus_scaling;
	bool support_fde;		bool support_fde;
	@@ -3676,16 +3672,13 @@ static int __qseecom_enable_clk(enum qseecom_ce_hw_instance ce)
	int rc = 0;		int rc = 0;
	struct qseecom_clk *qclk = NULL;		struct qseecom_clk *qclk = NULL;

	if (qseecom.no_clock_support &&		if (qseecom.no_clock_support)
	((ce != CLK_UFS_ICE) \|\| (ce != CLK_SDCC_ICE)))
	return 0;		return 0;

	if (ce == CLK_QSEE)		if (ce == CLK_QSEE)
	qclk = &qseecom.qsee;		qclk = &qseecom.qsee;
	if (ce == CLK_CE_DRV)		if (ce == CLK_CE_DRV)
	qclk = &qseecom.ce_drv;		qclk = &qseecom.ce_drv;
	if ((ce == CLK_UFS_ICE) \|\| (ce == CLK_SDCC_ICE))
	qclk = &qseecom.ce_ice;

	if (qclk == NULL) {		if (qclk == NULL) {
	pr_err("CLK type not supported\n");		pr_err("CLK type not supported\n");
	@@ -3745,14 +3738,11 @@ static void __qseecom_disable_clk(enum qseecom_ce_hw_instance ce)
	{		{
	struct qseecom_clk *qclk;		struct qseecom_clk *qclk;

	if (qseecom.no_clock_support &&		if (qseecom.no_clock_support)
	((ce != CLK_UFS_ICE) \|\| ce != CLK_SDCC_ICE))
	return;		return;

	if (ce == CLK_QSEE)		if (ce == CLK_QSEE)
	qclk = &qseecom.qsee;		qclk = &qseecom.qsee;
	else if ((ce == CLK_UFS_ICE) \|\| (ce == CLK_SDCC_ICE))
	qclk = &qseecom.ce_ice;
	else		else
	qclk = &qseecom.ce_drv;		qclk = &qseecom.ce_drv;

	@@ -4502,82 +4492,28 @@ static int __qseecom_update_current_key_user_info(
	return ret;		return ret;
	}		}

	static int qseecom_get_vreg(void)
	{
	int ret = 0;
	if (!qseecom.is_regulator_available)
	return 0;
	if (qseecom.reg)
	return 0;
	qseecom.reg = devm_regulator_get(qseecom.pdev, "vdd-hba");
	if (IS_ERR(qseecom.reg)) {
	ret = PTR_ERR(qseecom.reg);
	dev_err(qseecom.pdev, "%s: %s get failed, err=%d\n",
	__func__, "vdd-hba-supply", ret);
	}
	return ret;
	}

	static int qseecom_enable_ice_setup(int usage)		static int qseecom_enable_ice_setup(int usage)
	{		{
	int ret = 0;		int ret = 0;
	if (usage == QSEOS_KM_USAGE_UFS_ICE_DISK_ENCRYPTION) {
	if (qseecom.ce_ice.instance == CLK_INVALID) {		if (usage == QSEOS_KM_USAGE_UFS_ICE_DISK_ENCRYPTION)
	if (__qseecom_init_clk(CLK_UFS_ICE)) {		ret = qcom_ice_setup_ice_hw("ufs", true);
	pr_err("Failed to get storage clocks\n");		else if (usage == QSEOS_KM_USAGE_SDCC_ICE_DISK_ENCRYPTION)
	ret = -1;		ret = qcom_ice_setup_ice_hw("sdcc", true);
	goto out;
	}
	}
	if (qseecom_get_vreg()) {
	pr_err("%s: Could not get regulator\n", __func__);
	ret = -1;
	goto out;
	}
	if (qseecom.is_regulator_available &&
	regulator_enable(qseecom.reg)) {
	pr_err("%s: Could not enable regulator\n",
	__func__);
	ret = -1;
	goto out;
	}
	__qseecom_enable_clk(CLK_UFS_ICE);
	} else if (usage == QSEOS_KM_USAGE_SDCC_ICE_DISK_ENCRYPTION) {
	if (qseecom.ce_ice.instance == CLK_INVALID) {
	if (__qseecom_init_clk(CLK_SDCC_ICE)) {
	pr_err("Failed to get storage clocks\n");
	ret = -1;
	goto out;
	}
	}
	__qseecom_enable_clk(CLK_SDCC_ICE);
	}
	out:
	return ret;		return ret;
	}		}

	static int qseecom_disable_ice_setup(int usage)		static int qseecom_disable_ice_setup(int usage)
	{		{
	int ret = 0;		int ret = 0;
	if (qseecom.ce_ice.instance == CLK_INVALID)
	return 0;

	if (usage == QSEOS_KM_USAGE_UFS_ICE_DISK_ENCRYPTION) {		if (usage == QSEOS_KM_USAGE_UFS_ICE_DISK_ENCRYPTION)
	__qseecom_disable_clk(CLK_UFS_ICE);		ret = qcom_ice_setup_ice_hw("ufs", false);
	if (!qseecom.reg)		else if (usage == QSEOS_KM_USAGE_SDCC_ICE_DISK_ENCRYPTION)
	goto out;		ret = qcom_ice_setup_ice_hw("sdcc", false);

	if (qseecom.is_regulator_available &&
	regulator_disable(qseecom.reg)) {
	pr_err("%s: Could not enable regulator\n",
	__func__);
	ret = -1;
	goto out;
	}
	} else if (usage == QSEOS_KM_USAGE_SDCC_ICE_DISK_ENCRYPTION) {
	__qseecom_disable_clk(CLK_SDCC_ICE);
	}
	out:
	return ret;		return ret;
	}		}

	@@ -6242,34 +6178,12 @@ static int __qseecom_init_clk(enum qseecom_ce_hw_instance ce)
	qclk->instance = CLK_CE_DRV;		qclk->instance = CLK_CE_DRV;
	break;		break;
	};		};
	case CLK_UFS_ICE: {
	core_clk_src = "ufs_core_clk_src";
	core_clk = "ufs_core_clk";
	iface_clk = "ufs_iface_clk";
	bus_clk = "ufs_bus_clk";
	qclk = &qseecom.ce_ice;
	qclk->instance = CLK_UFS_ICE;
	break;
	};
	case CLK_SDCC_ICE: {
	core_clk_src = "sdcc_core_clk_src";
	core_clk = "sdcc_core_clk";
	iface_clk = "sdcc_iface_clk";
	bus_clk = "sdcc_bus_clk";
	/* ce_ice is used for both UFS and SDCC based ICE because there
	* will be only one ICE instance on chip : UFS or EMMC
	*/
	qclk = &qseecom.ce_ice;
	qclk->instance = CLK_SDCC_ICE;
	break;
	}
	default:		default:
	pr_err("Invalid ce hw instance: %d!\n", ce);		pr_err("Invalid ce hw instance: %d!\n", ce);
	return -EIO;		return -EIO;
	}		}

	if (qseecom.no_clock_support &&		if (qseecom.no_clock_support) {
	(ce != CLK_SDCC_ICE \|\| ce != CLK_UFS_ICE)) {
	qclk->ce_core_clk = NULL;		qclk->ce_core_clk = NULL;
	qclk->ce_clk = NULL;		qclk->ce_clk = NULL;
	qclk->ce_bus_clk = NULL;		qclk->ce_bus_clk = NULL;
	@@ -6282,7 +6196,6 @@ static int __qseecom_init_clk(enum qseecom_ce_hw_instance ce)
	/* Get CE3 src core clk. */		/* Get CE3 src core clk. */
	qclk->ce_core_src_clk = clk_get(pdev, core_clk_src);		qclk->ce_core_src_clk = clk_get(pdev, core_clk_src);
	if (!IS_ERR(qclk->ce_core_src_clk)) {		if (!IS_ERR(qclk->ce_core_src_clk)) {
	if ((ce != CLK_UFS_ICE) \|\| (ce != CLK_SDCC_ICE)) {
	rc = clk_set_rate(qclk->ce_core_src_clk,		rc = clk_set_rate(qclk->ce_core_src_clk,
	qseecom.ce_opp_freq_hz);		qseecom.ce_opp_freq_hz);
	if (rc) {		if (rc) {
	@@ -6292,7 +6205,6 @@ static int __qseecom_init_clk(enum qseecom_ce_hw_instance ce)
	qseecom.ce_opp_freq_hz/CE_CLK_DIV);		qseecom.ce_opp_freq_hz/CE_CLK_DIV);
	return -EIO;		return -EIO;
	}		}
	}
	} else {		} else {
	pr_warn("Unable to get CE core src clk, set to NULL\n");		pr_warn("Unable to get CE core src clk, set to NULL\n");
	qclk->ce_core_src_clk = NULL;		qclk->ce_core_src_clk = NULL;
	@@ -6340,8 +6252,6 @@ static void __qseecom_deinit_clk(enum qseecom_ce_hw_instance ce)

	if (ce == CLK_QSEE)		if (ce == CLK_QSEE)
	qclk = &qseecom.qsee;		qclk = &qseecom.qsee;
	else if (ce == CLK_UFS_ICE \|\| ce == CLK_SDCC_ICE)
	qclk = &qseecom.ce_ice;
	else		else
	qclk = &qseecom.ce_drv;		qclk = &qseecom.ce_drv;

	@@ -6393,12 +6303,6 @@ static int qseecom_probe(struct platform_device *pdev)
	qseecom.ce_drv.ce_core_src_clk = NULL;		qseecom.ce_drv.ce_core_src_clk = NULL;
	qseecom.ce_drv.ce_bus_clk = NULL;		qseecom.ce_drv.ce_bus_clk = NULL;

	qseecom.ce_ice.instance = CLK_INVALID;
	qseecom.ce_ice.ce_core_clk = NULL;
	qseecom.ce_ice.ce_clk = NULL;
	qseecom.ce_ice.ce_core_src_clk = NULL;
	qseecom.ce_ice.ce_bus_clk = NULL;
	qseecom.ce_ice.clk_access_cnt = 0;

	rc = alloc_chrdev_region(&qseecom_device_no, 0, 1, QSEECOM_DEV);		rc = alloc_chrdev_region(&qseecom_device_no, 0, 1, QSEECOM_DEV);
	if (rc < 0) {		if (rc < 0) {
	@@ -6676,10 +6580,6 @@ static int qseecom_probe(struct platform_device *pdev)
	goto exit_destroy_hw_instance_list;		goto exit_destroy_hw_instance_list;
	}		}
	}		}
	if (!of_parse_phandle(pdev->dev.of_node, "vdd-hba-supply", 0))
	qseecom.is_regulator_available = false;
	else
	qseecom.is_regulator_available = true;
	} else {		} else {
	qseecom_platform_support = (struct msm_bus_scale_pdata *)		qseecom_platform_support = (struct msm_bus_scale_pdata *)
	pdev->dev.platform_data;		pdev->dev.platform_data;
	@@ -6770,13 +6670,6 @@ exit_irqrestore:
	if ((qseecom.qsee.instance != qseecom.ce_drv.instance) &&		if ((qseecom.qsee.instance != qseecom.ce_drv.instance) &&
	(qseecom.support_pfe \|\| qseecom.support_fde))		(qseecom.support_pfe \|\| qseecom.support_fde))
	__qseecom_deinit_clk(CLK_CE_DRV);		__qseecom_deinit_clk(CLK_CE_DRV);

	/*
	* both UFS and SDCC ICE clocks points to clk_ice. So it is safe
	* to call deinit on either one.
	*/
	if (qseecom.ce_ice.instance != CLK_INVALID)
	__qseecom_deinit_clk(CLK_UFS_ICE);
	}		}

	ion_client_destroy(qseecom.ion_clnt);		ion_client_destroy(qseecom.ion_clnt);

include/crypto/ice.h

+8 −0

Original line number	Original line	Diff line number	Diff line
	@@ -74,7 +74,15 @@ typedef void (ice_error_cb)(void , enum ice_error_code);

	struct qcom_ice_variant_ops qcom_ice_get_variant_ops(struct device_node node);		struct qcom_ice_variant_ops qcom_ice_get_variant_ops(struct device_node node);
	struct platform_device qcom_ice_get_pdevice(struct device_node node);		struct platform_device qcom_ice_get_pdevice(struct device_node node);

			#ifdef CONFIG_CRYPTO_DEV_QCOM_ICE
	int qcom_ice_setup_ice_hw(const char *, int);		int qcom_ice_setup_ice_hw(const char *, int);
			#else
			static inline int qcom_ice_setup_ice_hw(const char *, int)
			{
			return 0;
			}
			#endif

	struct qcom_ice_variant_ops {		struct qcom_ice_variant_ops {
	const char *name;		const char *name;