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Commit 5ef7008b authored by Vignesh R's avatar Vignesh R Committed by Sasha Levin
Browse files

ARM: dts: am43xx-clocks: Fix ehrpwm tbclk data on am43xx 



[ Upstream commit 7d53d25578486d65bd7cd242bc7816b40e55e62b ]

ehrpwm tbclk is wrongly modelled as deriving from dpll_per_m2_ck.
The TRM says tbclk is derived from SYSCLKOUT. SYSCLKOUT nothing but the
functional clock of pwmss (l4ls_gclk).
Fix this by changing source of ehrpwmx_tbclk to l4ls_gclk.

Fixes: 4da1c677 ("add tbclk data for ehrpwm")
Signed-off-by: default avatarVignesh R <vigneshr@ti.com>
Acked-by: default avatarTero Kristo <t-kristo@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
Signed-off-by: default avatarSasha Levin <sasha.levin@oracle.com>
parent 25d96d6b

arch/arm/boot/dts/am43xx-clocks.dtsi

+6 −6
Original line number Diff line number Diff line
@@ -107,7 +107,7 @@ 
	ehrpwm0_tbclk: ehrpwm0_tbclk {

		#clock-cells = <0>;

		compatible = "ti,gate-clock";

		clocks = <&dpll_per_m2_ck>;

		clocks = <&l4ls_gclk>;

		ti,bit-shift = <0>;

		reg = <0x0664>;

	};
@@ -115,7 +115,7 @@ 
	ehrpwm1_tbclk: ehrpwm1_tbclk {

		#clock-cells = <0>;

		compatible = "ti,gate-clock";

		clocks = <&dpll_per_m2_ck>;

		clocks = <&l4ls_gclk>;

		ti,bit-shift = <1>;

		reg = <0x0664>;

	};
@@ -123,7 +123,7 @@ 
	ehrpwm2_tbclk: ehrpwm2_tbclk {

		#clock-cells = <0>;

		compatible = "ti,gate-clock";

		clocks = <&dpll_per_m2_ck>;

		clocks = <&l4ls_gclk>;

		ti,bit-shift = <2>;

		reg = <0x0664>;

	};
@@ -131,7 +131,7 @@ 
	ehrpwm3_tbclk: ehrpwm3_tbclk {

		#clock-cells = <0>;

		compatible = "ti,gate-clock";

		clocks = <&dpll_per_m2_ck>;

		clocks = <&l4ls_gclk>;

		ti,bit-shift = <4>;

		reg = <0x0664>;

	};
@@ -139,7 +139,7 @@ 
	ehrpwm4_tbclk: ehrpwm4_tbclk {

		#clock-cells = <0>;

		compatible = "ti,gate-clock";

		clocks = <&dpll_per_m2_ck>;

		clocks = <&l4ls_gclk>;

		ti,bit-shift = <5>;

		reg = <0x0664>;

	};
@@ -147,7 +147,7 @@ 
	ehrpwm5_tbclk: ehrpwm5_tbclk {

		#clock-cells = <0>;

		compatible = "ti,gate-clock";

		clocks = <&dpll_per_m2_ck>;

		clocks = <&l4ls_gclk>;

		ti,bit-shift = <6>;

		reg = <0x0664>;

	};