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Commit 25d96d6b authored by Vignesh R's avatar Vignesh R Committed by Sasha Levin
Browse files

ARM: dts: am33xx-clocks: Fix ehrpwm tbclk data on am33xx 



[ Upstream commit 6e22616eba7e25fac5aa6cb6563471afa1815ec2 ]

ehrpwm tbclk is wrongly modelled as deriving from dpll_per_m2_ck.
The TRM says tbclk is derived from SYSCLKOUT. SYSCLKOUT nothing but the
functional clock of pwmss (l4ls_gclk).
Fix this by changing source of ehrpwmx_tbclk to l4ls_gclk.

Fixes: 9e100eba: ("Fix ehrpwm tbclk data")
Signed-off-by: default avatarVignesh R <vigneshr@ti.com>
Acked-by: default avatarTero Kristo <t-kristo@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
Signed-off-by: default avatarSasha Levin <sasha.levin@oracle.com>
parent 07554817

arch/arm/boot/dts/am33xx-clocks.dtsi

+3 −3
Original line number Diff line number Diff line
@@ -99,7 +99,7 @@ 
	ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 {

		#clock-cells = <0>;

		compatible = "ti,gate-clock";

		clocks = <&dpll_per_m2_ck>;

		clocks = <&l4ls_gclk>;

		ti,bit-shift = <0>;

		reg = <0x0664>;

	};
@@ -107,7 +107,7 @@ 
	ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 {

		#clock-cells = <0>;

		compatible = "ti,gate-clock";

		clocks = <&dpll_per_m2_ck>;

		clocks = <&l4ls_gclk>;

		ti,bit-shift = <1>;

		reg = <0x0664>;

	};
@@ -115,7 +115,7 @@ 
	ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 {

		#clock-cells = <0>;

		compatible = "ti,gate-clock";

		clocks = <&dpll_per_m2_ck>;

		clocks = <&l4ls_gclk>;

		ti,bit-shift = <2>;

		reg = <0x0664>;

	};