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Commit 5e090ed7 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'soc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 

Pull late ARM soc platform updates from Olof Johansson:
 "This branch contains updates to OMAP and Marvell platforms (kirkwood,
  dove, mvebu) that came in after we had done the big multiplatform
  merges, so they were kept separate from the rest, and not separated
  into the traditional topics of cleanup/driver/platform features.

  For OMAP, the updates are:
   - Runtime PM conversions for the GPMC and RNG IP blocks
   - Preparation patches for the OMAP common clock framework conversion
   - clkdev alias additions required by other drivers
   - Performance Monitoring Unit (PMU) support for OMAP2, 3, and
     non-4430 OMAP4
   - OMAP hwmod code and data improvements
   - Preparation patches for the IOMMU runtime PM conversion
   - Preparation patches for OMAP4 full-chip retention support

  For Kirkwood/Dove/mvebu:
   - New driver for "address decoder controller" for mvebu, which is a
     piece of hardware that configures addressable devices and
     peripherals.  First user is the boot rom aperture on armada XP
     since it is needed for SMP support.
   - New device tree bindings for peripherals such as gpio-fan, iconnect
     nand, mv_cesa and the above address decoder controller.
   - Some defconfig updates, mostly to enable new DT boards and a few
     drivers.
   - New drivers using the pincontrol subsystem for dove, kirkwood and
     mvebu
   - New clean gpio driver for mvebu"

* tag 'soc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (98 commits)
  ARM: mvebu: fix build breaks from multi-platform conversion
  ARM: OMAP4460/4470: PMU: Enable PMU for OMAP4460/70
  ARM: OMAP2+: PMU: Add runtime PM support
  ARM: OMAP4430: PMU: prepare to create PMU device via HWMOD
  ARM: OMAP2+: PMU: Convert OMAP2/3 devices to use HWMOD
  ARM: OMAP3: hwmod data: Add debugss HWMOD data
  ARM: OMAP2+: clockdomain/hwmod: add workaround for EMU clockdomain idle problems
  ARM: OMAP: Add a timer attribute for timers that can interrupt the DSP
  hwrng: OMAP: remove SoC restrictions from driver registration
  ARM: OMAP: split OMAP1, OMAP2+ RNG device registration
  hwrng: OMAP: convert to use runtime PM
  hwrng: OMAP: store per-device data in per-device variables, not file statics
  ARM: OMAP2xxx: hwmod/CM: add RNG integration data
  ARM: OMAP2+: gpmc: minimal driver support
  ARM: OMAP2+: gpmc: Adapt to HWMOD
  ARM: OMAP2/3: hwmod data: add gpmc
  ARM: OMAP4: hwmod data: add mmu hwmod for ipu and dsp
  ARM: OMAP3: hwmod data: add mmu data for iva and isp
  ARM: OMAP: iommu: fix including iommu.h without IOMMU_API selected
  ARM: OMAP4: hwmod data: add missing HWMOD_NO_IDLEST flags to some PRCM IP blocks
  ...
parents 84424026 54d69df5

Documentation/devicetree/bindings/crypto/mv_cesa.txt

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Marvell Cryptographic Engines And Security Accelerator



Required properties:

- compatible : should be "marvell,orion-crypto"

- reg : base physical address of the engine and length of memory mapped

        region, followed by base physical address of sram and its memory

        length

- reg-names : "regs" , "sram";

- interrupts : interrupt number



Examples:



	crypto@30000 {

		compatible = "marvell,orion-crypto";

		reg = <0x30000 0x10000>,

		      <0x4000000 0x800>;

		reg-names = "regs" , "sram";

		interrupts = <22>;

		status = "okay";

	};

Documentation/devicetree/bindings/gpio/gpio-fan.txt

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Bindings for fan connected to GPIO lines



Required properties:

- compatible : "gpio-fan"

- gpios: Specifies the pins that map to bits in the control value,

  ordered MSB-->LSB.

- gpio-fan,speed-map: A mapping of possible fan RPM speeds and the

  control value that should be set to achieve them. This array

  must have the RPM values in ascending order.



Optional properties:

- alarm-gpios: This pin going active indicates something is wrong with

  the fan, and a udev event will be fired.



Examples:



	gpio_fan {

		compatible = "gpio-fan";

		gpios = <&gpio1 14 1

			 &gpio1 13 1>;

		gpio-fan,speed-map = <0    0

				      3000 1

				      6000 2>;

		alarm-gpios = <&gpio1 15 1>;

	};

Documentation/devicetree/bindings/gpio/gpio-mvebu.txt

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* Marvell EBU GPIO controller



Required properties:



- compatible : Should be "marvell,orion-gpio", "marvell,mv78200-gpio"

  or "marvell,armadaxp-gpio". "marvell,orion-gpio" should be used for

  Orion, Kirkwood, Dove, Discovery (except MV78200) and Armada

  370. "marvell,mv78200-gpio" should be used for the Discovery

  MV78200. "marvel,armadaxp-gpio" should be used for all Armada XP

  SoCs (MV78230, MV78260, MV78460).



- reg: Address and length of the register set for the device. Only one

  entry is expected, except for the "marvell,armadaxp-gpio" variant

  for which two entries are expected: one for the general registers,

  one for the per-cpu registers.



- interrupts: The list of interrupts that are used for all the pins

  managed by this GPIO bank. There can be more than one interrupt

  (example: 1 interrupt per 8 pins on Armada XP, which means 4

  interrupts per bank of 32 GPIOs).



- interrupt-controller: identifies the node as an interrupt controller



- #interrupt-cells: specifies the number of cells needed to encode an

  interrupt source. Should be two.

  The first cell is the GPIO number.

  The second cell is used to specify flags:

    bits[3:0] trigger type and level flags:

      1 = low-to-high edge triggered.

      2 = high-to-low edge triggered.

      4 = active high level-sensitive.

      8 = active low level-sensitive.



- gpio-controller: marks the device node as a gpio controller



- ngpios: number of GPIOs this controller has



- #gpio-cells: Should be two. The first cell is the pin number. The

  second cell is reserved for flags, unused at the moment.



Example:



		gpio0: gpio@d0018100 {

			compatible = "marvell,armadaxp-gpio";

			reg = <0xd0018100 0x40>,

			    <0xd0018800 0x30>;

			ngpios = <32>;

			gpio-controller;

			#gpio-cells = <2>;

			interrupt-controller;

			#interrupt-cells = <2>;

			interrupts = <16>, <17>, <18>, <19>;

		};

Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt

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* Marvell Armada 370 SoC pinctrl driver for mpp



Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding

part and usage.



Required properties:

- compatible: "marvell,88f6710-pinctrl"



Available mpp pins/groups and functions:

Note: brackets (x) are not part of the mpp name for marvell,function and given

only for more detailed description in this document.



name          pins     functions

================================================================================

mpp0          0        gpio, uart0(rxd)

mpp1          1        gpo, uart0(txd)

mpp2          2        gpio, i2c0(sck), uart0(txd)

mpp3          3        gpio, i2c0(sda), uart0(rxd)

mpp4          4        gpio, cpu_pd(vdd)

mpp5          5        gpo, ge0(txclko), uart1(txd), spi1(clk), audio(mclk)

mpp6          6        gpio, ge0(txd0), sata0(prsnt), tdm(rst), audio(sdo)

mpp7          7        gpo, ge0(txd1), tdm(tdx), audio(lrclk)

mpp8          8        gpio, ge0(txd2), uart0(rts), tdm(drx), audio(bclk)

mpp9          9        gpo, ge0(txd3), uart1(txd), sd0(clk), audio(spdifo)

mpp10         10       gpio, ge0(txctl), uart0(cts), tdm(fsync), audio(sdi)

mpp11         11       gpio, ge0(rxd0), uart1(rxd), sd0(cmd), spi0(cs1),

                       sata1(prsnt), spi1(cs1)

mpp12         12       gpio, ge0(rxd1), i2c1(sda), sd0(d0), spi1(cs0),

                       audio(spdifi)

mpp13         13       gpio, ge0(rxd2), i2c1(sck), sd0(d1), tdm(pclk),

                       audio(rmclk)

mpp14         14       gpio, ge0(rxd3), pcie(clkreq0), sd0(d2), spi1(mosi),

                       spi0(cs2)

mpp15         15       gpio, ge0(rxctl), pcie(clkreq1), sd0(d3), spi1(miso),

                       spi0(cs3)

mpp16         16       gpio, ge0(rxclk), uart1(rxd), tdm(int), audio(extclk)

mpp17         17       gpo, ge(mdc)

mpp18         18       gpio, ge(mdio)

mpp19         19       gpio, ge0(txclk), ge1(txclkout), tdm(pclk)

mpp20         20       gpo, ge0(txd4), ge1(txd0)

mpp21         21       gpo, ge0(txd5), ge1(txd1), uart1(txd)

mpp22         22       gpo, ge0(txd6), ge1(txd2), uart0(rts)

mpp23         23       gpo, ge0(txd7), ge1(txd3), spi1(mosi)

mpp24         24       gpio, ge0(col), ge1(txctl), spi1(cs0)

mpp25         25       gpio, ge0(rxerr), ge1(rxd0), uart1(rxd)

mpp26         26       gpio, ge0(crs), ge1(rxd1), spi1(miso)

mpp27         27       gpio, ge0(rxd4), ge1(rxd2), uart0(cts)

mpp28         28       gpio, ge0(rxd5), ge1(rxd3)

mpp29         29       gpio, ge0(rxd6), ge1(rxctl), i2c1(sda)

mpp30         30       gpio, ge0(rxd7), ge1(rxclk), i2c1(sck)

mpp31         31       gpio, tclk, ge0(txerr)

mpp32         32       gpio, spi0(cs0)

mpp33         33       gpio, dev(bootcs), spi0(cs0)

mpp34         34       gpo, dev(wen0), spi0(mosi)

mpp35         35       gpo, dev(oen), spi0(sck)

mpp36         36       gpo, dev(a1), spi0(miso)

mpp37         37       gpo, dev(a0), sata0(prsnt)

mpp38         38       gpio, dev(ready), uart1(cts), uart0(cts)

mpp39         39       gpo, dev(ad0), audio(spdifo)

mpp40         40       gpio, dev(ad1), uart1(rts), uart0(rts)

mpp41         41       gpio, dev(ad2), uart1(rxd)

mpp42         42       gpo, dev(ad3), uart1(txd)

mpp43         43       gpo, dev(ad4), audio(bclk)

mpp44         44       gpo, dev(ad5), audio(mclk)

mpp45         45       gpo, dev(ad6), audio(lrclk)

mpp46         46       gpo, dev(ad7), audio(sdo)

mpp47         47       gpo, dev(ad8), sd0(clk), audio(spdifo)

mpp48         48       gpio, dev(ad9), uart0(rts), sd0(cmd), sata1(prsnt),

                       spi0(cs1)

mpp49         49       gpio, dev(ad10), pcie(clkreq1), sd0(d0), spi1(cs0),

                       audio(spdifi)

mpp50         50       gpio, dev(ad11), uart0(cts), sd0(d1), spi1(miso),

                       audio(rmclk)

mpp51         51       gpio, dev(ad12), i2c1(sda), sd0(d2), spi1(mosi)

mpp52         52       gpio, dev(ad13), i2c1(sck), sd0(d3), spi1(sck)

mpp53         53       gpio, dev(ad14), sd0(clk), tdm(pclk), spi0(cs2),

                       pcie(clkreq1)

mpp54         54       gpo, dev(ad15), tdm(dtx)

mpp55         55       gpio, dev(cs1), uart1(txd), tdm(rst), sata1(prsnt),

                       sata0(prsnt)

mpp56         56       gpio, dev(cs2), uart1(cts), uart0(cts), spi0(cs3),

                       pcie(clkreq0), spi1(cs1)

mpp57         57       gpio, dev(cs3), uart1(rxd), tdm(fsync), sata0(prsnt),

                       audio(sdo)

mpp58         58       gpio, dev(cs0), uart1(rts), tdm(int), audio(extclk),

                       uart0(rts)

mpp59         59       gpo, dev(ale0), uart1(rts), uart0(rts), audio(bclk)

mpp60         60       gpio, dev(ale1), uart1(rxd), sata0(prsnt), pcie(rst-out),

                       audio(sdi)

mpp61         61       gpo, dev(wen1), uart1(txd), audio(rclk)

mpp62         62       gpio, dev(a2), uart1(cts), tdm(drx), pcie(clkreq0),

                       audio(mclk), uart0(cts)

mpp63         63       gpo, spi0(sck), tclk

mpp64         64       gpio, spi0(miso), spi0-1(cs1)

mpp65         65       gpio, spi0(mosi), spi0-1(cs2)

Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt

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* Marvell Armada XP SoC pinctrl driver for mpp



Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding

part and usage.



Required properties:

- compatible: "marvell,mv78230-pinctrl", "marvell,mv78260-pinctrl",

              "marvell,mv78460-pinctrl"



This driver supports all Armada XP variants, i.e. mv78230, mv78260, and mv78460.



Available mpp pins/groups and functions:

Note: brackets (x) are not part of the mpp name for marvell,function and given

only for more detailed description in this document.



* Marvell Armada XP (all variants)



name          pins     functions

================================================================================

mpp0          0        gpio, ge0(txclko), lcd(d0)

mpp1          1        gpio, ge0(txd0), lcd(d1)

mpp2          2        gpio, ge0(txd1), lcd(d2)

mpp3          3        gpio, ge0(txd2), lcd(d3)

mpp4          4        gpio, ge0(txd3), lcd(d4)

mpp5          5        gpio, ge0(txctl), lcd(d5)

mpp6          6        gpio, ge0(rxd0), lcd(d6)

mpp7          7        gpio, ge0(rxd1), lcd(d7)

mpp8          8        gpio, ge0(rxd2), lcd(d8)

mpp9          9        gpio, ge0(rxd3), lcd(d9)

mpp10         10       gpio, ge0(rxctl), lcd(d10)

mpp11         11       gpio, ge0(rxclk), lcd(d11)

mpp12         12       gpio, ge0(txd4), ge1(txd0), lcd(d12)

mpp13         13       gpio, ge0(txd5), ge1(txd1), lcd(d13)

mpp14         14       gpio, ge0(txd6), ge1(txd2), lcd(d15)

mpp15         15       gpio, ge0(txd7), ge1(txd3), lcd(d16)

mpp16         16       gpio, ge0(txd7), ge1(txd3), lcd(d16)

mpp17         17       gpio, ge0(col), ge1(txctl), lcd(d17)

mpp18         18       gpio, ge0(rxerr), ge1(rxd0), lcd(d18), ptp(trig)

mpp19         19       gpio, ge0(crs), ge1(rxd1), lcd(d19), ptp(evreq)

mpp20         20       gpio, ge0(rxd4), ge1(rxd2), lcd(d20), ptp(clk)

mpp21         21       gpio, ge0(rxd5), ge1(rxd3), lcd(d21), mem(bat)

mpp22         22       gpio, ge0(rxd6), ge1(rxctl), lcd(d22), sata0(prsnt)

mpp23         23       gpio, ge0(rxd7), ge1(rxclk), lcd(d23), sata1(prsnt)

mpp24         24       gpio, lcd(hsync), sata1(prsnt), nf(bootcs-re), tdm(rst)

mpp25         25       gpio, lcd(vsync), sata0(prsnt), nf(bootcs-we), tdm(pclk)

mpp26         26       gpio, lcd(clk), tdm(fsync), vdd(cpu1-pd)

mpp27         27       gpio, lcd(e), tdm(dtx), ptp(trig)

mpp28         28       gpio, lcd(pwm), tdm(drx), ptp(evreq)

mpp29         29       gpio, lcd(ref-clk), tdm(int0), ptp(clk), vdd(cpu0-pd)

mpp30         30       gpio, tdm(int1), sd0(clk)

mpp31         31       gpio, tdm(int2), sd0(cmd), vdd(cpu0-pd)

mpp32         32       gpio, tdm(int3), sd0(d0), vdd(cpu1-pd)

mpp33         33       gpio, tdm(int4), sd0(d1), mem(bat)

mpp34         34       gpio, tdm(int5), sd0(d2), sata0(prsnt)

mpp35         35       gpio, tdm(int6), sd0(d3), sata1(prsnt)

mpp36         36       gpio, spi(mosi)

mpp37         37       gpio, spi(miso)

mpp38         38       gpio, spi(sck)

mpp39         39       gpio, spi(cs0)

mpp40         40       gpio, spi(cs1), uart2(cts), lcd(vga-hsync), vdd(cpu1-pd),

                       pcie(clkreq0)

mpp41         41       gpio, spi(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt),

                       pcie(clkreq1)

mpp42         42       gpio, uart2(rxd), uart0(cts), tdm(int7), tdm-1(timer),

                       vdd(cpu0-pd)

mpp43         43       gpio, uart2(txd), uart0(rts), spi(cs3), pcie(rstout),

                       vdd(cpu2-3-pd){1}

mpp44         44       gpio, uart2(cts), uart3(rxd), spi(cs4), pcie(clkreq2),

                       mem(bat)

mpp45         45       gpio, uart2(rts), uart3(txd), spi(cs5), sata1(prsnt)

mpp46         46       gpio, uart3(rts), uart1(rts), spi(cs6), sata0(prsnt)

mpp47         47       gpio, uart3(cts), uart1(cts), spi(cs7), pcie(clkreq3),

                       ref(clkout)

mpp48         48       gpio, tclk, dev(burst/last)



* Marvell Armada XP (mv78260 and mv78460 only)



name          pins     functions

================================================================================

mpp49         49       gpio, dev(we3)

mpp50         50       gpio, dev(we2)

mpp51         51       gpio, dev(ad16)

mpp52         52       gpio, dev(ad17)

mpp53         53       gpio, dev(ad18)

mpp54         54       gpio, dev(ad19)

mpp55         55       gpio, dev(ad20), vdd(cpu0-pd)

mpp56         56       gpio, dev(ad21), vdd(cpu1-pd)

mpp57         57       gpio, dev(ad22), vdd(cpu2-3-pd){1}

mpp58         58       gpio, dev(ad23)

mpp59         59       gpio, dev(ad24)

mpp60         60       gpio, dev(ad25)

mpp61         61       gpio, dev(ad26)

mpp62         62       gpio, dev(ad27)

mpp63         63       gpio, dev(ad28)

mpp64         64       gpio, dev(ad29)

mpp65         65       gpio, dev(ad30)

mpp66         66       gpio, dev(ad31)



Notes:

* {1} vdd(cpu2-3-pd) only available on mv78460.