Loading arch/arm/boot/dts/qcom/msm8996-v1.dtsi +11 −0 Original line number Diff line number Diff line Loading @@ -156,6 +156,17 @@ }; }; &ufsphy1 { clock-names = "ref_clk_src", "ref_clk", "tx_iface_clk", "rx_iface_clk"; clocks = <&clock_gcc clk_ln_bb_clk>, <&clock_gcc clk_gcc_ufs_clkref_clk>, <&clock_gcc clk_gcc_ufs_tx_cfg_clk>, <&clock_gcc clk_gcc_ufs_rx_cfg_clk>; }; &ufs1 { clock-names = "core_clk_src", Loading arch/arm/boot/dts/qcom/msm8996.dtsi +2 −6 Original line number Diff line number Diff line Loading @@ -1233,13 +1233,9 @@ vddp-ref-clk-max-microamp = <100>; vddp-ref-clk-always-on; clock-names = "ref_clk_src", "ref_clk", "tx_iface_clk", "rx_iface_clk"; "ref_clk"; clocks = <&clock_gcc clk_ln_bb_clk>, <&clock_gcc clk_gcc_ufs_clkref_clk>, <&clock_gcc clk_gcc_ufs_tx_cfg_clk>, <&clock_gcc clk_gcc_ufs_rx_cfg_clk>; <&clock_gcc clk_gcc_ufs_clkref_clk>; status = "disabled"; }; Loading Loading
arch/arm/boot/dts/qcom/msm8996-v1.dtsi +11 −0 Original line number Diff line number Diff line Loading @@ -156,6 +156,17 @@ }; }; &ufsphy1 { clock-names = "ref_clk_src", "ref_clk", "tx_iface_clk", "rx_iface_clk"; clocks = <&clock_gcc clk_ln_bb_clk>, <&clock_gcc clk_gcc_ufs_clkref_clk>, <&clock_gcc clk_gcc_ufs_tx_cfg_clk>, <&clock_gcc clk_gcc_ufs_rx_cfg_clk>; }; &ufs1 { clock-names = "core_clk_src", Loading
arch/arm/boot/dts/qcom/msm8996.dtsi +2 −6 Original line number Diff line number Diff line Loading @@ -1233,13 +1233,9 @@ vddp-ref-clk-max-microamp = <100>; vddp-ref-clk-always-on; clock-names = "ref_clk_src", "ref_clk", "tx_iface_clk", "rx_iface_clk"; "ref_clk"; clocks = <&clock_gcc clk_ln_bb_clk>, <&clock_gcc clk_gcc_ufs_clkref_clk>, <&clock_gcc clk_gcc_ufs_tx_cfg_clk>, <&clock_gcc clk_gcc_ufs_rx_cfg_clk>; <&clock_gcc clk_gcc_ufs_clkref_clk>; status = "disabled"; }; Loading