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Commit 5d79677d authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Configure I2C node for msmthorium"

parents 8727d7c7 7e6897ee

arch/arm/boot/dts/qcom/msmthorium-pinctrl.dtsi

+59 −0
Original line number Diff line number Diff line
@@ -50,5 +50,64 @@ 


		};



		i2c2 {

			i2c2_default: i2c2_default {

				/* active state */

				mux {

					pins = "gpio6", "gpio7";

					function = "blsp_i2c2";

				};



				config {

					pins = "gpio6", "gpio7";

					drive-strength = <2>;

					bias-disable;

				};

			};



			i2c2_sleep: i2c2_sleep {

				/* suspended state */

				mux {

					pins = "gpio6", "gpio7";

					function = "gpio";

				};



				config {

					pins = "gpio6", "gpio7";

					drive-strength = <2>;

					bias-pull-down;

				};

			};

		};



		i2c5 {

			i2c5_default: i2c5_default {

				/* active state */

				mux {

					pins = "gpio18", "gpio19";

					function = "blsp_i2c5";

				};



				config {

					pins = "gpio18", "gpio19";

					drive-strength = <2>;

					bias-disable;

				};

			};



			i2c5_sleep: i2c5_sleep {

				/* suspended state */

				mux {

					pins = "gpio18", "gpio19";

					function = "gpio";

				};



				config {

					pins = "gpio18", "gpio19";

					drive-strength = <2>;

					bias-pull-down;

				};

			};

		};

	};

};

arch/arm/boot/dts/qcom/msmthorium.dtsi

+68 −0
Original line number Diff line number Diff line
@@ -80,6 +80,8 @@ 
		smd11 = &smdtty_data11;

		smd21 = &smdtty_data21;

		smd36 = &smdtty_loopback;

		i2c2 = &i2c_2;

		i2c5 = &i2c_5;

	};



	soc: soc { };
@@ -202,6 +204,72 @@ 
		clock-names = "core_clk", "iface_clk";

	};



	dma_blsp1: qcom,sps-dma@7884000 { /* BLSP1 */

		#dma-cells = <4>;

		compatible = "qcom,sps-dma";

		reg = <0x7884000 0x1f000>;

		interrupts = <0 238 0>;

		qcom,summing-threshold = <10>;

	};



	dma_blsp2: qcom,sps-dma@7ac4000 { /* BLSP2 */

		#dma-cells = <4>;

		compatible = "qcom,sps-dma";

		reg = <0x7ac4000 0x1f000>;

		interrupts = <0 239 0>;

		qcom,summing-threshold = <10>;

	};



	i2c_2: i2c@78b6000 { /* BLSP1 QUP2 */

		compatible = "qcom,i2c-msm-v2";

		#address-cells = <1>;

		#size-cells = <0>;

		reg-names = "qup_phys_addr";

		reg = <0x78b6000 0x600>;

		interrupt-names = "qup_irq";

		interrupts = <0 96 0>;

		qcom,clk-freq-out = <400000>;

		qcom,clk-freq-in  = <19200000>;

		clock-names = "iface_clk", "core_clk";

		clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,

			<&clock_gcc clk_gcc_blsp1_qup2_i2c_apps_clk>;



		pinctrl-names = "i2c_default", "i2c_sleep";

		pinctrl-0 = <&i2c2_default>;

		pinctrl-1 = <&i2c2_sleep>;

		qcom,noise-rjct-scl = <0>;

		qcom,noise-rjct-sda = <0>;

		qcom,master-id = <86>;

		dmas = <&dma_blsp1 6 64 0x20000020 0x20>,

			<&dma_blsp1 7 32 0x20000020 0x20>;

		dma-names = "tx", "rx";

	};



	i2c_5: i2c@7af5000 { /* BLSP2 QUP1 */

		compatible = "qcom,i2c-msm-v2";

		#address-cells = <1>;

		#size-cells = <0>;

		reg-names = "qup_phys_addr";

		reg = <0x7af5000 0x600>;

		interrupt-names = "qup_irq";

		interrupts = <0 299 0>;

		qcom,clk-freq-out = <400000>;

		qcom,clk-freq-in  = <19200000>;

		clock-names = "iface_clk", "core_clk";

		clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>,

			<&clock_gcc clk_gcc_blsp2_qup1_i2c_apps_clk>;



		pinctrl-names = "i2c_default", "i2c_sleep";

		pinctrl-0 = <&i2c5_default>;

		pinctrl-1 = <&i2c5_sleep>;

		qcom,noise-rjct-scl = <0>;

		qcom,noise-rjct-sda = <0>;

		qcom,master-id = <86>;

		dmas = <&dma_blsp2 4 64 0x20000020 0x20>,

			<&dma_blsp2 5 32 0x20000020 0x20>;

		dma-names = "tx", "rx";

	};



	clock_gcc: qcom,gcc {

		compatible = "qcom,dummycc";

		#clock-cells = <1>;