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Commit 5b777674 authored by Christian König's avatar Christian König Committed by Sasha Levin
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drm/radeon: workaround for CP HW bug on CIK 



commit a9c73a0e022c33954835e66fec3cd744af90ec98 upstream.

Emit the EOP twice to avoid cache flushing problems.

Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarSasha Levin <sasha.levin@oracle.com>
parent fee477d5

drivers/gpu/drm/radeon/cik.c

+15 −1
Original line number Diff line number Diff line
@@ -3880,7 +3880,21 @@ void cik_fence_gfx_ring_emit(struct radeon_device *rdev, 
	struct radeon_ring *ring = &rdev->ring[fence->ring];

	u64 addr = rdev->fence_drv[fence->ring].gpu_addr;



	/* EVENT_WRITE_EOP - flush caches, send int */

	/* Workaround for cache flush problems. First send a dummy EOP

	 * event down the pipe with seq one below.

	 */

	radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));

	radeon_ring_write(ring, (EOP_TCL1_ACTION_EN |

				 EOP_TC_ACTION_EN |

				 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |

				 EVENT_INDEX(5)));

	radeon_ring_write(ring, addr & 0xfffffffc);

	radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) |

				DATA_SEL(1) | INT_SEL(0));

	radeon_ring_write(ring, fence->seq - 1);

	radeon_ring_write(ring, 0);



	/* Then send the real EOP event down the pipe. */

	radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));

	radeon_ring_write(ring, (EOP_TCL1_ACTION_EN |

				 EOP_TC_ACTION_EN |