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Commit fee477d5 authored by Alex Deucher's avatar Alex Deucher Committed by Sasha Levin
Browse files

drm/radeon: only enable kv/kb dpm interrupts once v3 



commit 410af8d7285a0b96314845c75c39fd612b755688 upstream.

Enable at init and disable on fini. Workaround for hardware problems.

v2 (chk): extend commit message
v3: add new function

Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: Christian König <christian.koenig@amd.com> (v2)
Signed-off-by: default avatarSasha Levin <sasha.levin@oracle.com>
parent 22d4d7e7

drivers/gpu/drm/radeon/cik.c

+0 −21
Original line number Diff line number Diff line
@@ -7295,7 +7295,6 @@ int cik_irq_set(struct radeon_device *rdev) 
	u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;

	u32 grbm_int_cntl = 0;

	u32 dma_cntl, dma_cntl1;

	u32 thermal_int;



	if (!rdev->irq.installed) {

		WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
@@ -7332,13 +7331,6 @@ int cik_irq_set(struct radeon_device *rdev) 
	cp_m2p2 = RREG32(CP_ME2_PIPE2_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;

	cp_m2p3 = RREG32(CP_ME2_PIPE3_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;



	if (rdev->flags & RADEON_IS_IGP)

		thermal_int = RREG32_SMC(CG_THERMAL_INT_CTRL) &

			~(THERM_INTH_MASK | THERM_INTL_MASK);

	else

		thermal_int = RREG32_SMC(CG_THERMAL_INT) &

			~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);



	/* enable CP interrupts on all rings */

	if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {

		DRM_DEBUG("cik_irq_set: sw int gfx\n");
@@ -7496,14 +7488,6 @@ int cik_irq_set(struct radeon_device *rdev) 
		hpd6 |= DC_HPDx_INT_EN;

	}



	if (rdev->irq.dpm_thermal) {

		DRM_DEBUG("dpm thermal\n");

		if (rdev->flags & RADEON_IS_IGP)

			thermal_int |= THERM_INTH_MASK | THERM_INTL_MASK;

		else

			thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;

	}



	WREG32(CP_INT_CNTL_RING0, cp_int_cntl);



	WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, dma_cntl);
@@ -7557,11 +7541,6 @@ int cik_irq_set(struct radeon_device *rdev) 
	WREG32(DC_HPD5_INT_CONTROL, hpd5);

	WREG32(DC_HPD6_INT_CONTROL, hpd6);



	if (rdev->flags & RADEON_IS_IGP)

		WREG32_SMC(CG_THERMAL_INT_CTRL, thermal_int);

	else

		WREG32_SMC(CG_THERMAL_INT, thermal_int);



	return 0;

}

drivers/gpu/drm/radeon/kv_dpm.c

+15 −2
Original line number Diff line number Diff line
@@ -1169,6 +1169,19 @@ void kv_dpm_enable_bapm(struct radeon_device *rdev, bool enable) 
	}

}



static void kv_enable_thermal_int(struct radeon_device *rdev, bool enable)

{

	u32 thermal_int;



	thermal_int = RREG32_SMC(CG_THERMAL_INT_CTRL);

	if (enable)

		thermal_int |= THERM_INTH_MASK | THERM_INTL_MASK;

	else

		thermal_int &= ~(THERM_INTH_MASK | THERM_INTL_MASK);

	WREG32_SMC(CG_THERMAL_INT_CTRL, thermal_int);



}



int kv_dpm_enable(struct radeon_device *rdev)

{

	struct kv_power_info *pi = kv_get_pi(rdev);
@@ -1280,8 +1293,7 @@ int kv_dpm_late_enable(struct radeon_device *rdev) 
			DRM_ERROR("kv_set_thermal_temperature_range failed\n");

			return ret;

		}

		rdev->irq.dpm_thermal = true;

		radeon_irq_set(rdev);

		kv_enable_thermal_int(rdev, true);

	}



	/* powerdown unused blocks for now */
@@ -1312,6 +1324,7 @@ void kv_dpm_disable(struct radeon_device *rdev) 
	kv_stop_dpm(rdev);

	kv_enable_ulv(rdev, false);

	kv_reset_am(rdev);

	kv_enable_thermal_int(rdev, false);



	kv_update_current_ps(rdev, rdev->pm.dpm.boot_ps);

}