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Commit 582c7fbe authored by navin patidar's avatar navin patidar Committed by Greg Kroah-Hartman
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staging: rtl8188eu: HalPwrSeqCmd.h: Remove unnecessary comments. 



Signed-off-by: default avatarnavin patidar <navin.patidar@gmail.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 8bfdbb1b

drivers/staging/rtl8188eu/include/HalPwrSeqCmd.h

+35 −73
Original line number Diff line number Diff line
@@ -22,68 +22,32 @@ 


#include <drv_types.h>



/*---------------------------------------------*/

/* 3 The value of cmd: 4 bits */

/*---------------------------------------------*/

/* The value of cmd: 4 bits */

#define PWR_CMD_READ		0x00

     /*  offset: the read register offset */

     /*  msk: the mask of the read value */

     /*  value: N/A, left by 0 */

     /*  note: dirver shall implement this function by read & msk */



#define PWR_CMD_WRITE		0x01

     /*  offset: the read register offset */

     /*  msk: the mask of the write bits */

     /*  value: write value */

     /*  note: driver shall implement this cmd by read & msk after write */



#define PWR_CMD_POLLING		0x02

     /*  offset: the read register offset */

     /*  msk: the mask of the polled value */

     /*  value: the value to be polled, masked by the msd field. */

     /*  note: driver shall implement this cmd by */

     /*  do{ */

     /*  if ( (Read(offset) & msk) == (value & msk) ) */

     /*  break; */

     /*  } while (not timeout); */



#define PWR_CMD_DELAY		0x03

     /*  offset: the value to delay */

     /*  msk: N/A */

     /*  value: the unit of delay, 0: us, 1: ms */



#define PWR_CMD_END		0x04

     /*  offset: N/A */

     /*  msk: N/A */

     /*  value: N/A */



/*---------------------------------------------*/

/* 3 The value of base: 4 bits */

/*---------------------------------------------*/

/* The value of base: 4 bits */

/*  define the base address of each block */

#define PWR_BASEADDR_MAC	0x00

#define PWR_BASEADDR_USB	0x01

#define PWR_BASEADDR_PCIE	0x02

#define PWR_BASEADDR_SDIO	0x03



/*---------------------------------------------*/

/* 3 The value of interface_msk: 4 bits */

/*---------------------------------------------*/

/* The value of interface_msk: 4 bits */

#define PWR_INTF_SDIO_MSK	BIT(0)

#define PWR_INTF_USB_MSK	BIT(1)

#define PWR_INTF_PCI_MSK	BIT(2)

#define PWR_INTF_ALL_MSK	(BIT(0)|BIT(1)|BIT(2)|BIT(3))



/*---------------------------------------------*/

/* 3 The value of fab_msk: 4 bits */

/*---------------------------------------------*/

/* The value of fab_msk: 4 bits */

#define PWR_FAB_TSMC_MSK	BIT(0)

#define PWR_FAB_UMC_MSK		BIT(1)

#define PWR_FAB_ALL_MSK		(BIT(0)|BIT(1)|BIT(2)|BIT(3))



/*---------------------------------------------*/

/* 3 The value of cut_msk: 8 bits */

/*---------------------------------------------*/

/* The value of cut_msk: 8 bits */

#define PWR_CUT_TESTCHIP_MSK	BIT(0)

#define PWR_CUT_A_MSK		BIT(1)

#define PWR_CUT_B_MSK		BIT(2)
@@ -120,8 +84,6 @@ struct wl_pwr_cfg { 
#define GET_PWR_CFG_MASK(__PWR_CMD)		__PWR_CMD.msk

#define GET_PWR_CFG_VALUE(__PWR_CMD)		__PWR_CMD.value





/*	Prototype of protected function. */

u8 rtl88eu_pwrseqcmdparsing(struct adapter *padapter, u8 cut_vers, u8 fab_vers,

			    u8 ifacetype, struct wl_pwr_cfg pwrcfgCmd[]);