Loading drivers/platform/msm/ep_pcie/ep_pcie_com.h +1 −0 Original line number Diff line number Diff line Loading @@ -43,6 +43,7 @@ #define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT 0x1A8 #define PCIE20_PARF_Q2A_FLUSH 0x1AC #define PCIE20_PARF_LTSSM 0x1B0 #define PCIE20_PARF_CFG_BITS 0x210 #define PCIE20_PARF_LTR_MSI_EXIT_L1SS 0x214 #define PCIE20_PARF_INT_ALL_STATUS 0x224 #define PCIE20_PARF_INT_ALL_CLEAR 0x228 Loading drivers/platform/msm/ep_pcie/ep_pcie_core.c +3 −0 Original line number Diff line number Diff line Loading @@ -519,6 +519,9 @@ static void ep_pcie_core_init(struct ep_pcie_dev_t *dev, bool configured) /* Set AUX power to be on */ ep_pcie_write_mask(dev->parf + PCIE20_PARF_SYS_CTRL, 0, BIT(4)); /* Request to exit from L1SS for MSI and LTR MSG */ ep_pcie_write_mask(dev->parf + PCIE20_PARF_CFG_BITS, 0, BIT(1)); EP_PCIE_DBG(dev, "Initial: CLASS_CODE_REVISION_ID:0x%x; HDR_TYPE:0x%x\n", readl_relaxed(dev->dm_core + PCIE20_CLASS_CODE_REVISION_ID), Loading Loading
drivers/platform/msm/ep_pcie/ep_pcie_com.h +1 −0 Original line number Diff line number Diff line Loading @@ -43,6 +43,7 @@ #define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT 0x1A8 #define PCIE20_PARF_Q2A_FLUSH 0x1AC #define PCIE20_PARF_LTSSM 0x1B0 #define PCIE20_PARF_CFG_BITS 0x210 #define PCIE20_PARF_LTR_MSI_EXIT_L1SS 0x214 #define PCIE20_PARF_INT_ALL_STATUS 0x224 #define PCIE20_PARF_INT_ALL_CLEAR 0x228 Loading
drivers/platform/msm/ep_pcie/ep_pcie_core.c +3 −0 Original line number Diff line number Diff line Loading @@ -519,6 +519,9 @@ static void ep_pcie_core_init(struct ep_pcie_dev_t *dev, bool configured) /* Set AUX power to be on */ ep_pcie_write_mask(dev->parf + PCIE20_PARF_SYS_CTRL, 0, BIT(4)); /* Request to exit from L1SS for MSI and LTR MSG */ ep_pcie_write_mask(dev->parf + PCIE20_PARF_CFG_BITS, 0, BIT(1)); EP_PCIE_DBG(dev, "Initial: CLASS_CODE_REVISION_ID:0x%x; HDR_TYPE:0x%x\n", readl_relaxed(dev->dm_core + PCIE20_CLASS_CODE_REVISION_ID), Loading