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Commit 8f6e7837 authored by Yan He's avatar Yan He Committed by Gerrit - the friendly Code Review server
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msm: ep_pcie: enable L1ss exit for sending message 



Enable the request to exit L1ss when send MSI or LTR message.

Change-Id: I68a506bd22f531acabc0c313f4839f53d59682cf
Signed-off-by: default avatarYan He <yanhe@codeaurora.org>
parent 3016bb41

drivers/platform/msm/ep_pcie/ep_pcie_com.h

+1 −0
Original line number Diff line number Diff line
@@ -43,6 +43,7 @@ 
#define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT      0x1A8

#define PCIE20_PARF_Q2A_FLUSH          0x1AC

#define PCIE20_PARF_LTSSM              0x1B0

#define PCIE20_PARF_CFG_BITS           0x210

#define PCIE20_PARF_LTR_MSI_EXIT_L1SS  0x214

#define PCIE20_PARF_INT_ALL_STATUS     0x224

#define PCIE20_PARF_INT_ALL_CLEAR      0x228

drivers/platform/msm/ep_pcie/ep_pcie_core.c

+3 −0
Original line number Diff line number Diff line
@@ -519,6 +519,9 @@ static void ep_pcie_core_init(struct ep_pcie_dev_t *dev, bool configured) 
	/* Set AUX power to be on */

	ep_pcie_write_mask(dev->parf + PCIE20_PARF_SYS_CTRL, 0, BIT(4));



	/* Request to exit from L1SS for MSI and LTR MSG */

	ep_pcie_write_mask(dev->parf + PCIE20_PARF_CFG_BITS, 0, BIT(1));



	EP_PCIE_DBG(dev,

		"Initial: CLASS_CODE_REVISION_ID:0x%x; HDR_TYPE:0x%x\n",

		readl_relaxed(dev->dm_core + PCIE20_CLASS_CODE_REVISION_ID),