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Commit 4d817d3d authored by Andre Przywara's avatar Andre Przywara Committed by Sasha Levin
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arm64: add Cortex-A53 cache errata workaround



The ARM errata 819472, 826319, 827319 and 824069 define the same
workaround for these hardware issues in certain Cortex-A53 parts.
Use the new alternatives framework and the CPU MIDR detection to
patch "cache clean" into "cache clean and invalidate" instructions if
an affected CPU is detected at runtime.

Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
[will: add __maybe_unused to squash gcc warning]
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>

Cc: <stable@vger.kernel.org> # v3.18.y
(cherry picked from commit 301bcfac42897dbd1b0b3c1be49f24654a1bc49e)
Signed-off-by: default avatarKevin Hilman <khilman@linaro.org>
Signed-off-by: default avatarSasha Levin <sasha.levin@oracle.com>
parent da767e54
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