clk: msm: mdss: fix precision loss in VCO clock rate calculation

As per the DSI programming guide, the generated VCO clock comes out
to be same as the calculated vco clock rate as per the below equations.

div_fb = calc_vco_clk / ref_clk_to_pll
generated_vco_clk = div_fb * ref_clk_to_pll

But due to precision loss during implementation of this, some of the
DSI PLL register values might slightly deviate from the expected
values. Add change to fix this by equating the generated VCO clock to
same value as calculated VCO rate.

Change-Id: I478f45766c50ea88c102a87f95be47ec79a74b9a
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>