Loading arch/arm/boot/dts/qcom/msm8996-bus.dtsi +2 −2 Original line number Diff line number Diff line Loading @@ -186,8 +186,8 @@ qcom,setrate-only-clk; qcom,bus-type = <1>; clock-names = "bus_clk", "bus_a_clk"; clocks = <&clock_mmss clk_mmss_mmagic_ahb_clk>, <&clock_mmss clk_mmss_mmagic_ahb_clk>; clocks = <&clock_mmss clk_ahb_clk_src>, <&clock_mmss clk_ahb_clk_src>; bus-gdsc-supply = <&gdsc_mmagic_bimc>; bus-a-gdsc-supply = <&gdsc_mmagic_bimc>; }; Loading drivers/clk/msm/clock-mmss-8996.c +1 −1 Original line number Diff line number Diff line Loading @@ -1649,7 +1649,7 @@ static struct rcg_clk video_subcore1_clk_src = { static struct branch_clk mmss_mmagic_ahb_clk = { .cbcr_reg = MMSS_MMSS_MMAGIC_AHB_CBCR, .has_sibling = 0, .has_sibling = 1, .check_enable_bit = true, .base = &virt_base, .no_halt_check_on_disable = true, Loading Loading
arch/arm/boot/dts/qcom/msm8996-bus.dtsi +2 −2 Original line number Diff line number Diff line Loading @@ -186,8 +186,8 @@ qcom,setrate-only-clk; qcom,bus-type = <1>; clock-names = "bus_clk", "bus_a_clk"; clocks = <&clock_mmss clk_mmss_mmagic_ahb_clk>, <&clock_mmss clk_mmss_mmagic_ahb_clk>; clocks = <&clock_mmss clk_ahb_clk_src>, <&clock_mmss clk_ahb_clk_src>; bus-gdsc-supply = <&gdsc_mmagic_bimc>; bus-a-gdsc-supply = <&gdsc_mmagic_bimc>; }; Loading
drivers/clk/msm/clock-mmss-8996.c +1 −1 Original line number Diff line number Diff line Loading @@ -1649,7 +1649,7 @@ static struct rcg_clk video_subcore1_clk_src = { static struct branch_clk mmss_mmagic_ahb_clk = { .cbcr_reg = MMSS_MMSS_MMAGIC_AHB_CBCR, .has_sibling = 0, .has_sibling = 1, .check_enable_bit = true, .base = &virt_base, .no_halt_check_on_disable = true, Loading