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Commit 28cd4eab authored by Deepak Katragadda's avatar Deepak Katragadda
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clk: msm: clock: Do not allow setting rate on mmss_mmagic_ahb_clk 



Remove support to allow setting a rate on the ahb_clk_src
using the mmss_mmagic_ahb_clk. The bus driver should be the
only one setting the AHB rate by using the ahb_clk_src
reference directly.

Change-Id: I4426af89c2ae567b246790b8a3218001456c15ec
Signed-off-by: default avatarDeepak Katragadda <dkatraga@codeaurora.org>
parent 7d54fbdb

arch/arm/boot/dts/qcom/msm8996-bus.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -186,8 +186,8 @@ 
			qcom,setrate-only-clk;

			qcom,bus-type = <1>;

			clock-names = "bus_clk", "bus_a_clk";

			clocks = <&clock_mmss clk_mmss_mmagic_ahb_clk>,

			     <&clock_mmss clk_mmss_mmagic_ahb_clk>;

			clocks = <&clock_mmss clk_ahb_clk_src>,

			     <&clock_mmss clk_ahb_clk_src>;

			bus-gdsc-supply = <&gdsc_mmagic_bimc>;

			bus-a-gdsc-supply = <&gdsc_mmagic_bimc>;

		};

drivers/clk/msm/clock-mmss-8996.c

+1 −1
Original line number Diff line number Diff line
@@ -1649,7 +1649,7 @@ static struct rcg_clk video_subcore1_clk_src = { 


static struct branch_clk mmss_mmagic_ahb_clk = {

	.cbcr_reg = MMSS_MMSS_MMAGIC_AHB_CBCR,

	.has_sibling = 0,

	.has_sibling = 1,

	.check_enable_bit = true,

	.base = &virt_base,

	.no_halt_check_on_disable = true,