Loading arch/arm/boot/dts/qcom/msm8920.dtsi +54 −0 Original line number Original line Diff line number Diff line Loading @@ -193,3 +193,57 @@ /delete-property/ qcom,cpr-init-voltage-adjustment; /delete-property/ qcom,cpr-init-voltage-adjustment; /delete-property/ qcom,cpr-enable; /delete-property/ qcom,cpr-enable; }; }; &funnel_apss { coresight-child-ports = <3>; }; &soc { /delete-node/ cti@6124000; cti_modem_cpu0: cti@6128000 { compatible = "arm,coresight-cti"; reg = <0x6128000 0x1000>; reg-names = "cti-base"; coresight-id = <51>; coresight-name = "coresight-cti-modem-cpu0"; coresight-nr-inports = <0>; clocks = <&clock_gcc clk_qdss_clk>, <&clock_gcc clk_qdss_a_clk>; clock-names = "core_clk", "core_a_clk"; }; /* MSS_SCL */ modem_etm0 { coresight-child-ports = <2>; }; cti_modem_cpu1: cti@6124000 { compatible = "arm,coresight-cti"; reg = <0x6124000 0x1000>; reg-names = "cti-base"; coresight-id = <52>; coresight-name = "coresight-cti-modem-cpu1"; coresight-nr-inports = <0>; clocks = <&clock_gcc clk_qdss_clk>, <&clock_gcc clk_qdss_a_clk>; clock-names = "core_clk", "core_a_clk"; }; /* MSS_VEC */ modem_etm1 { compatible = "qcom,coresight-remote-etm"; coresight-id = <53>; coresight-name = "coresight-modem-etm1"; coresight-nr-inports = <0>; coresight-outports = <0>; coresight-child-list = <&funnel_right>; coresight-child-ports = <1>; qcom,inst-id = <11>; }; }; arch/arm/boot/dts/qcom/msm8940.dtsi +17 −2 Original line number Original line Diff line number Diff line Loading @@ -287,12 +287,27 @@ }; }; &soc { &soc { cti_modem_cpu1: cti@6128000{ /delete-node/ cti@6124000; cti_modem_cpu0: cti@6128000{ compatible = "arm,coresight-cti"; compatible = "arm,coresight-cti"; reg = <0x6128000 0x1000>; reg = <0x6128000 0x1000>; reg-names = "cti-base"; reg-names = "cti-base"; coresight-id = <59>; coresight-id = <59>; coresight-name = "coresight-cti-modem-cpu0"; coresight-nr-inports = <0>; clocks = <&clock_gcc clk_qdss_clk>, <&clock_gcc clk_qdss_a_clk>; clock-names = "core_clk", "core_a_clk"; }; cti_modem_cpu1: cti@6124000{ compatible = "arm,coresight-cti"; reg = <0x6124000 0x1000>; reg-names = "cti-base"; coresight-id = <60>; coresight-name = "coresight-cti-modem-cpu1"; coresight-name = "coresight-cti-modem-cpu1"; coresight-nr-inports = <0>; coresight-nr-inports = <0>; Loading @@ -305,7 +320,7 @@ modem_etm1 { modem_etm1 { compatible = "qcom,coresight-remote-etm"; compatible = "qcom,coresight-remote-etm"; coresight-id = <60>; coresight-id = <61>; coresight-name = "coresight-modem-etm1"; coresight-name = "coresight-modem-etm1"; coresight-nr-inports = <0>; coresight-nr-inports = <0>; coresight-outports = <0>; coresight-outports = <0>; Loading arch/arm/boot/dts/qcom/msm8953-coresight.dtsi +4 −4 Original line number Original line Diff line number Diff line Loading @@ -751,9 +751,9 @@ clock-names = "core_clk", "core_a_clk"; clock-names = "core_clk", "core_a_clk"; }; }; cti_modem_cpu0: cti@6124000 { cti_modem_cpu0: cti@6128000 { compatible = "arm,coresight-cti"; compatible = "arm,coresight-cti"; reg = <0x6124000 0x1000>; reg = <0x6128000 0x1000>; reg-names = "cti-base"; reg-names = "cti-base"; coresight-id = <44>; coresight-id = <44>; Loading @@ -765,9 +765,9 @@ clock-names = "core_clk", "core_a_clk"; clock-names = "core_clk", "core_a_clk"; }; }; cti_modem_cpu1: cti@6128000{ cti_modem_cpu1: cti@6124000{ compatible = "arm,coresight-cti"; compatible = "arm,coresight-cti"; reg = <0x6128000 0x1000>; reg = <0x6124000 0x1000>; reg-names = "cti-base"; reg-names = "cti-base"; coresight-id = <45>; coresight-id = <45>; Loading Loading
arch/arm/boot/dts/qcom/msm8920.dtsi +54 −0 Original line number Original line Diff line number Diff line Loading @@ -193,3 +193,57 @@ /delete-property/ qcom,cpr-init-voltage-adjustment; /delete-property/ qcom,cpr-init-voltage-adjustment; /delete-property/ qcom,cpr-enable; /delete-property/ qcom,cpr-enable; }; }; &funnel_apss { coresight-child-ports = <3>; }; &soc { /delete-node/ cti@6124000; cti_modem_cpu0: cti@6128000 { compatible = "arm,coresight-cti"; reg = <0x6128000 0x1000>; reg-names = "cti-base"; coresight-id = <51>; coresight-name = "coresight-cti-modem-cpu0"; coresight-nr-inports = <0>; clocks = <&clock_gcc clk_qdss_clk>, <&clock_gcc clk_qdss_a_clk>; clock-names = "core_clk", "core_a_clk"; }; /* MSS_SCL */ modem_etm0 { coresight-child-ports = <2>; }; cti_modem_cpu1: cti@6124000 { compatible = "arm,coresight-cti"; reg = <0x6124000 0x1000>; reg-names = "cti-base"; coresight-id = <52>; coresight-name = "coresight-cti-modem-cpu1"; coresight-nr-inports = <0>; clocks = <&clock_gcc clk_qdss_clk>, <&clock_gcc clk_qdss_a_clk>; clock-names = "core_clk", "core_a_clk"; }; /* MSS_VEC */ modem_etm1 { compatible = "qcom,coresight-remote-etm"; coresight-id = <53>; coresight-name = "coresight-modem-etm1"; coresight-nr-inports = <0>; coresight-outports = <0>; coresight-child-list = <&funnel_right>; coresight-child-ports = <1>; qcom,inst-id = <11>; }; };
arch/arm/boot/dts/qcom/msm8940.dtsi +17 −2 Original line number Original line Diff line number Diff line Loading @@ -287,12 +287,27 @@ }; }; &soc { &soc { cti_modem_cpu1: cti@6128000{ /delete-node/ cti@6124000; cti_modem_cpu0: cti@6128000{ compatible = "arm,coresight-cti"; compatible = "arm,coresight-cti"; reg = <0x6128000 0x1000>; reg = <0x6128000 0x1000>; reg-names = "cti-base"; reg-names = "cti-base"; coresight-id = <59>; coresight-id = <59>; coresight-name = "coresight-cti-modem-cpu0"; coresight-nr-inports = <0>; clocks = <&clock_gcc clk_qdss_clk>, <&clock_gcc clk_qdss_a_clk>; clock-names = "core_clk", "core_a_clk"; }; cti_modem_cpu1: cti@6124000{ compatible = "arm,coresight-cti"; reg = <0x6124000 0x1000>; reg-names = "cti-base"; coresight-id = <60>; coresight-name = "coresight-cti-modem-cpu1"; coresight-name = "coresight-cti-modem-cpu1"; coresight-nr-inports = <0>; coresight-nr-inports = <0>; Loading @@ -305,7 +320,7 @@ modem_etm1 { modem_etm1 { compatible = "qcom,coresight-remote-etm"; compatible = "qcom,coresight-remote-etm"; coresight-id = <60>; coresight-id = <61>; coresight-name = "coresight-modem-etm1"; coresight-name = "coresight-modem-etm1"; coresight-nr-inports = <0>; coresight-nr-inports = <0>; coresight-outports = <0>; coresight-outports = <0>; Loading
arch/arm/boot/dts/qcom/msm8953-coresight.dtsi +4 −4 Original line number Original line Diff line number Diff line Loading @@ -751,9 +751,9 @@ clock-names = "core_clk", "core_a_clk"; clock-names = "core_clk", "core_a_clk"; }; }; cti_modem_cpu0: cti@6124000 { cti_modem_cpu0: cti@6128000 { compatible = "arm,coresight-cti"; compatible = "arm,coresight-cti"; reg = <0x6124000 0x1000>; reg = <0x6128000 0x1000>; reg-names = "cti-base"; reg-names = "cti-base"; coresight-id = <44>; coresight-id = <44>; Loading @@ -765,9 +765,9 @@ clock-names = "core_clk", "core_a_clk"; clock-names = "core_clk", "core_a_clk"; }; }; cti_modem_cpu1: cti@6128000{ cti_modem_cpu1: cti@6124000{ compatible = "arm,coresight-cti"; compatible = "arm,coresight-cti"; reg = <0x6128000 0x1000>; reg = <0x6124000 0x1000>; reg-names = "cti-base"; reg-names = "cti-base"; coresight-id = <45>; coresight-id = <45>; Loading