Loading arch/arm/boot/dts/qcom/mdm9607-regulator.dtsi +1 −1 Original line number Diff line number Diff line Loading @@ -358,7 +358,7 @@ qcom,cpr-init-voltage-as-ceiling; qcom,cpr-corner-frequency-map = <1 400000000>, <2 806400000>, <2 800000000>, <3 998400000>, <4 1094400000>, <5 1190400000>, Loading arch/arm/boot/dts/qcom/mdm9607.dtsi +6 −3 Original line number Diff line number Diff line Loading @@ -276,7 +276,8 @@ clock-names = "clk-1", "clk-5"; qcom,speed4-bin-v0 = < 0 0>, < 806400000 2>, < 400000000 1>, < 800000000 2>, < 998400000 3>, < 1094400000 4>, < 1190400000 5>, Loading Loading @@ -304,7 +305,8 @@ cpubw-cpufreq { target-dev = <&cpubw>; cpu-to-dev-map = < 806400 915>, < 400000 732>, < 800000 915>, < 998400 1145>, < 1094400 1831>, < 1305600 2291>; Loading @@ -326,7 +328,8 @@ clocks = <&clock_cpu clk_a7ssmux>; clock-names = "cpu0_clk"; qcom,cpufreq-table = < 806400 >, < 400000 >, < 800000 >, < 998400 >, < 1094400 >, < 1190400 >, Loading Loading
arch/arm/boot/dts/qcom/mdm9607-regulator.dtsi +1 −1 Original line number Diff line number Diff line Loading @@ -358,7 +358,7 @@ qcom,cpr-init-voltage-as-ceiling; qcom,cpr-corner-frequency-map = <1 400000000>, <2 806400000>, <2 800000000>, <3 998400000>, <4 1094400000>, <5 1190400000>, Loading
arch/arm/boot/dts/qcom/mdm9607.dtsi +6 −3 Original line number Diff line number Diff line Loading @@ -276,7 +276,8 @@ clock-names = "clk-1", "clk-5"; qcom,speed4-bin-v0 = < 0 0>, < 806400000 2>, < 400000000 1>, < 800000000 2>, < 998400000 3>, < 1094400000 4>, < 1190400000 5>, Loading Loading @@ -304,7 +305,8 @@ cpubw-cpufreq { target-dev = <&cpubw>; cpu-to-dev-map = < 806400 915>, < 400000 732>, < 800000 915>, < 998400 1145>, < 1094400 1831>, < 1305600 2291>; Loading @@ -326,7 +328,8 @@ clocks = <&clock_cpu clk_a7ssmux>; clock-names = "cpu0_clk"; qcom,cpufreq-table = < 806400 >, < 400000 >, < 800000 >, < 998400 >, < 1094400 >, < 1190400 >, Loading