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Commit 618dd680 authored by Jaydeep Sen's avatar Jaydeep Sen Committed by Taniya Das
Browse files

ARM: dts: msm: Add support for 400MHz as ACPU for MDM9607 



Add 400MHz in the speed-bin and cpufreq node to support it as a scaling
and available frequency for cpu clock. Update the frequency of 806.4MHz to
be now derived from GPLL0.

Change-Id: I9e3edd6564935c7bdfadd109e5652a81b3d8b2b6
Signed-off-by: default avatarJaydeep Sen <jsen@codeaurora.org>
parent 162066de

arch/arm/boot/dts/qcom/mdm9607-regulator.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -358,7 +358,7 @@ 
		qcom,cpr-init-voltage-as-ceiling;

		qcom,cpr-corner-frequency-map =

					<1 400000000>,

					<2 806400000>,

					<2 800000000>,

					<3 998400000>,

					<4 1094400000>,

					<5 1190400000>,

arch/arm/boot/dts/qcom/mdm9607.dtsi

+6 −3
Original line number Diff line number Diff line
@@ -276,7 +276,8 @@ 
		clock-names = "clk-1", "clk-5";

		qcom,speed4-bin-v0 =

				<          0 0>,

				<  806400000 2>,

				<  400000000 1>,

				<  800000000 2>,

				<  998400000 3>,

				< 1094400000 4>,

				< 1190400000 5>,
@@ -304,7 +305,8 @@ 
		cpubw-cpufreq {

			target-dev = <&cpubw>;

			cpu-to-dev-map =

				 <  806400   915>,

				 <  400000   732>,

				 <  800000   915>,

				 <  998400  1145>,

				 < 1094400  1831>,

				 < 1305600  2291>;
@@ -326,7 +328,8 @@ 
		clocks = <&clock_cpu  clk_a7ssmux>;

		clock-names = "cpu0_clk";

		qcom,cpufreq-table =

				<  806400 >,

				<  400000 >,

				<  800000 >,

				<  998400 >,

				< 1094400 >,

				< 1190400 >,