spi: spi_qsd: Modify the FIFO mode read/writes

The driver currently shifts the byte order when writing/reading to the
QUP output/input data registers in FIFO mode.
This shouldn't be done, as by design the QUP cores transmit bytes in
network order and also the driver code for FIFO mode isn't consistent for
the cases where the DMA moves data to the QUP data registers.

Change-Id: I13d378ab1015cb2068fbdb24414da24372ea90cc
Signed-off-by: Girish Mahadevan <girishm@codeaurora.org>