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Commit 41e18aa1 authored by Hanumant Singh's avatar Hanumant Singh Committed by Puja Gupta
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irqchip: GICv3: Check if GIC register access is controlled 



Add support to configure ITS registers only if higher
exception levels have not already configured them.

Change-Id: I45eaa51e56e034d011cf41d8b924fb674f63447d
Signed-off-by: default avatarHanumant Singh <hanumant@codeaurora.org>
Signed-off-by: default avatarPuja Gupta <pujag@codeaurora.org>
parent ff7c61dc

drivers/irqchip/Kconfig

+7 −0
Original line number Diff line number Diff line
@@ -31,6 +31,13 @@ config ARM_GIC_V3_ITS 
	bool

	select PCI_MSI_IRQ_DOMAIN



config ARM_GIC_V3_ACL

	bool "GICv3 Access control"

	depends on ARM_GIC_V3

	help

	  Access to GIC ITS address space is controlled by EL2.

	  Kernel has no permission to access ITS



config ARM_NVIC

	bool

	select IRQ_DOMAIN

drivers/irqchip/irq-gic-v3.c

+4 −2
Original line number Diff line number Diff line
@@ -546,7 +546,8 @@ static void gic_cpu_init(void) 
	gic_cpu_config(rbase, gic_redist_wait_for_rwp);



	/* Give LPIs a spin */

	if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis())

	if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis() &&

					!IS_ENABLED(CONFIG_ARM_GIC_V3_ACL))

		its_cpu_init();



	/* initialise system registers */
@@ -959,7 +960,8 @@ static int __init gic_of_init(struct device_node *node, struct device_node *pare 
	set_handle_irq(gic_handle_irq);



	gic_chip.flags |= gic_arch_extn.flags;

	if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis())

	if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis() &&

					!IS_ENABLED(CONFIG_ARM_GIC_V3_ACL))

		its_init(node, &gic_data.rdists, gic_data.domain);



	gic_smp_init();