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Commit 39eda2ab authored by Linus Torvalds's avatar Linus Torvalds
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Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc 

Pull powerpc updates from Ben Herrenschmidt:
 "Here's the powerpc batch for this merge window.  Some of the
  highlights are:

   - A bunch of endian fixes ! We don't have full LE support yet in that
     release but this contains a lot of fixes all over arch/powerpc to
     use the proper accessors, call the firmware with the right endian
     mode, etc...

   - A few updates to our "powernv" platform (non-virtualized, the one
     to run KVM on), among other, support for bridging the P8 LPC bus
     for UARTs, support and some EEH fixes.

   - Some mpc51xx clock API cleanups in preparation for a clock API
     overhaul

   - A pile of cleanups of our old math emulation code, including better
     support for using it to emulate optional FP instructions on
     embedded chips that otherwise have a HW FPU.

   - Some infrastructure in selftest, for powerpc now, but could be
     generalized, initially used by some tests for our perf instruction
     counting code.

   - A pile of fixes for hotplug on pseries (that was seriously
     bitrotting)

   - The usual slew of freescale embedded updates, new boards, 64-bit
     hiberation support, e6500 core PMU support, etc..."

* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (146 commits)
  powerpc: Correct FSCR bit definitions
  powerpc/xmon: Fix printing of set of CPUs in xmon
  powerpc/pseries: Move lparcfg.c to platforms/pseries
  powerpc/powernv: Return secondary CPUs to firmware on kexec
  powerpc/btext: Fix CONFIG_PPC_EARLY_DEBUG_BOOTX on ppc32
  powerpc: Cleanup handling of the DSCR bit in the FSCR register
  powerpc/pseries: Child nodes are not detached by dlpar_detach_node
  powerpc/pseries: Add mising of_node_put in delete_dt_node
  powerpc/pseries: Make dlpar_configure_connector parent node aware
  powerpc/pseries: Do all node initialization in dlpar_parse_cc_node
  powerpc/pseries: Fix parsing of initial node path in update_dt_node
  powerpc/pseries: Pack update_props_workarea to map correctly to rtas buffer header
  powerpc/pseries: Fix over writing of rtas return code in update_dt_node
  powerpc/pseries: Fix creation of loop in device node property list
  powerpc: Skip emulating & leave interrupts off for kernel program checks
  powerpc: Add more exception trampolines for hypervisor exceptions
  powerpc: Fix location and rename exception trampolines
  powerpc: Add more trap names to xmon
  powerpc/pseries: Add a warning in the case of cross-cpu VPA registration
  powerpc: Update the 00-Index in Documentation/powerpc
  ...
parents 2e515bf0 9f24b0c9

Documentation/devicetree/bindings/crypto/fsl-sec6.txt

0 → 100644
+157 −0
Original line number Diff line number Diff line 
SEC 6 is as Freescale's Cryptographic Accelerator and Assurance Module (CAAM).

Currently Freescale powerpc chip C29X is embeded with SEC 6.

SEC 6 device tree binding include:

   -SEC 6 Node

   -Job Ring Node

   -Full Example



=====================================================================

SEC 6 Node



Description



    Node defines the base address of the SEC 6 block.

    This block specifies the address range of all global

    configuration registers for the SEC 6 block.

    For example, In C293, we could see three SEC 6 node.



PROPERTIES



   - compatible

      Usage: required

      Value type: <string>

      Definition: Must include "fsl,sec-v6.0".



   - fsl,sec-era

      Usage: optional

      Value type: <u32>

      Definition: A standard property. Define the 'ERA' of the SEC

          device.



   - #address-cells

       Usage: required

       Value type: <u32>

       Definition: A standard property.  Defines the number of cells

           for representing physical addresses in child nodes.



   - #size-cells

       Usage: required

       Value type: <u32>

       Definition: A standard property.  Defines the number of cells

           for representing the size of physical addresses in

           child nodes.



   - reg

      Usage: required

      Value type: <prop-encoded-array>

      Definition: A standard property.  Specifies the physical

          address and length of the SEC 6 configuration registers.



   - ranges

       Usage: required

       Value type: <prop-encoded-array>

       Definition: A standard property.  Specifies the physical address

           range of the SEC 6.0 register space (-SNVS not included).  A

           triplet that includes the child address, parent address, &

           length.



   Note: All other standard properties (see the ePAPR) are allowed

   but are optional.



EXAMPLE

	crypto@a0000 {

		compatible = "fsl,sec-v6.0";

		fsl,sec-era = <6>;

		#address-cells = <1>;

		#size-cells = <1>;

		reg = <0xa0000 0x20000>;

		ranges = <0 0xa0000 0x20000>;

	};



=====================================================================

Job Ring (JR) Node



    Child of the crypto node defines data processing interface to SEC 6

    across the peripheral bus for purposes of processing

    cryptographic descriptors. The specified address

    range can be made visible to one (or more) cores.

    The interrupt defined for this node is controlled within

    the address range of this node.



  - compatible

      Usage: required

      Value type: <string>

      Definition: Must include "fsl,sec-v6.0-job-ring".



  - reg

      Usage: required

      Value type: <prop-encoded-array>

      Definition: Specifies a two JR parameters:  an offset from

           the parent physical address and the length the JR registers.



   - interrupts

      Usage: required

      Value type: <prop_encoded-array>

      Definition:  Specifies the interrupts generated by this

           device.  The value of the interrupts property

           consists of one interrupt specifier. The format

           of the specifier is defined by the binding document

           describing the node's interrupt parent.



EXAMPLE

	jr@1000 {

		compatible = "fsl,sec-v6.0-job-ring";

		reg = <0x1000 0x1000>;

		interrupts = <49 2 0 0>;

	};



===================================================================

Full Example



Since some chips may contain more than one SEC, the dtsi contains

only the node contents, not the node itself.  A chip using the SEC

should include the dtsi inside each SEC node.  Example:



In qoriq-sec6.0.dtsi:



	compatible = "fsl,sec-v6.0";

	fsl,sec-era = <6>;

	#address-cells = <1>;

	#size-cells = <1>;



	jr@1000 {

		compatible = "fsl,sec-v6.0-job-ring",

			     "fsl,sec-v5.2-job-ring",

			     "fsl,sec-v5.0-job-ring",

			     "fsl,sec-v4.4-job-ring",

			     "fsl,sec-v4.0-job-ring";

		reg	   = <0x1000 0x1000>;

	};



	jr@2000 {

		compatible = "fsl,sec-v6.0-job-ring",

			     "fsl,sec-v5.2-job-ring",

			     "fsl,sec-v5.0-job-ring",

			     "fsl,sec-v4.4-job-ring",

			     "fsl,sec-v4.0-job-ring";

		reg	   = <0x2000 0x1000>;

	};



In the C293 device tree, we add the include of public property:



	crypto@a0000 {

		/include/ "qoriq-sec6.0.dtsi"

	}



	crypto@a0000 {

		reg = <0xa0000 0x20000>;

		ranges = <0 0xa0000 0x20000>;



		jr@1000 {

			interrupts = <49 2 0 0>;

		};



		jr@2000 {

			interrupts = <50 2 0 0>;

		};

	};

Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt

+41 −12
Original line number Diff line number Diff line 
* Freescale MSI interrupt controller



Required properties:

- compatible : compatible list, contains 2 entries,

  first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572,

  etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" depending on

  the parent type.

- compatible : compatible list, may contain one or two entries

  The first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572,

  etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" or

  "fsl,mpic-msi-v4.3" depending on the parent type and version. If mpic

  version is 4.3, the number of MSI registers is increased to 16, MSIIR1 is

  provided to access these 16 registers, and compatible "fsl,mpic-msi-v4.3"

  should be used. The first entry is optional; the second entry is

  required.



- reg : It may contain one or two regions. The first region should contain

  the address and the length of the shared message interrupt register set.

  The second region should contain the address of aliased MSIIR register for

  platforms that have such an alias.



- msi-available-ranges: use <start count> style section to define which

  msi interrupt can be used in the 256 msi interrupts. This property is

  optional, without this, all the 256 MSI interrupts can be used.

  Each available range must begin and end on a multiple of 32 (i.e.

  no splitting an individual MSI register or the associated PIC interrupt).

  The second region should contain the address of aliased MSIIR or MSIIR1

  register for platforms that have such an alias, if using MSIIR1, the second

  region must be added because different MSI group has different MSIIR1 offset.



- interrupts : each one of the interrupts here is one entry per 32 MSIs,

  and routed to the host interrupt controller. the interrupts should
@@ -28,6 +27,14 @@ Required properties: 
  to MPIC.



Optional properties:

- msi-available-ranges: use <start count> style section to define which

  msi interrupt can be used in the 256 msi interrupts. This property is

  optional, without this, all the MSI interrupts can be used.

  Each available range must begin and end on a multiple of 32 (i.e.

  no splitting an individual MSI register or the associated PIC interrupt).

  MPIC v4.3 does not support this property because the 32 interrupts of an

  individual register are not continuous when using MSIIR1.



- msi-address-64: 64-bit PCI address of the MSIIR register. The MSIIR register

  is used for MSI messaging.  The address of MSIIR in PCI address space is

  the MSI message address.
@@ -54,6 +61,28 @@ Example: 
		interrupt-parent = <&mpic>;

	};



	msi@41600 {

		compatible = "fsl,mpic-msi-v4.3";

		reg = <0x41600 0x200 0x44148 4>;

		interrupts = <

			0xe0 0 0 0

			0xe1 0 0 0

			0xe2 0 0 0

			0xe3 0 0 0

			0xe4 0 0 0

			0xe5 0 0 0

			0xe6 0 0 0

			0xe7 0 0 0

			0x100 0 0 0

			0x101 0 0 0

			0x102 0 0 0

			0x103 0 0 0

			0x104 0 0 0

			0x105 0 0 0

			0x106 0 0 0

			0x107 0 0 0>;

	};



The Freescale hypervisor and msi-address-64

-------------------------------------------

Normally, PCI devices have access to all of CCSR via an ATMU mapping.  The

Documentation/powerpc/00-INDEX

+11 −0
Original line number Diff line number Diff line
@@ -5,13 +5,20 @@ please mail me. 


00-INDEX

	- this file

bootwrapper.txt

	- Information on how the powerpc kernel is wrapped for boot on various

	  different platforms.

cpu_features.txt

	- info on how we support a variety of CPUs with minimal compile-time

	options.

eeh-pci-error-recovery.txt

	- info on PCI Bus EEH Error Recovery

firmware-assisted-dump.txt

	- Documentation on the firmware assisted dump mechanism "fadump".

hvcs.txt

	- IBM "Hypervisor Virtual Console Server" Installation Guide

kvm_440.txt

	- Various notes on the implementation of KVM for PowerPC 440.

mpc52xx.txt

	- Linux 2.6.x on MPC52xx family

pmu-ebb.txt
@@ -19,3 +26,7 @@ pmu-ebb.txt 
qe_firmware.txt

	- describes the layout of firmware binaries for the Freescale QUICC

	  Engine and the code that parses and uploads the microcode therein.

ptrace.txt

	- Information on the ptrace interfaces for hardware debug registers.

transactional_memory.txt

	- Overview of the Power8 transactional memory support.

arch/powerpc/Kconfig

+20 −0
Original line number Diff line number Diff line
@@ -312,6 +312,26 @@ config MATH_EMULATION 
	  such as fsqrt on cores that do have an FPU but do not implement

	  them (such as Freescale BookE).



choice

	prompt "Math emulation options"

	default MATH_EMULATION_FULL

	depends on MATH_EMULATION



config	MATH_EMULATION_FULL

	bool "Emulate all the floating point instructions"

	---help---

	  Select this option will enable the kernel to support to emulate

	  all the floating point instructions. If your SoC doesn't have

	  a FPU, you should select this.



config MATH_EMULATION_HW_UNIMPLEMENTED

	bool "Just emulate the FPU unimplemented instructions"

	---help---

	  Select this if you know there does have a hardware FPU on your

	  SoC, but some floating point instructions are not implemented by that.



endchoice



config PPC_TRANSACTIONAL_MEM

       bool "Transactional Memory support for POWERPC"

       depends on PPC_BOOK3S_64

arch/powerpc/Makefile

+17 −1
Original line number Diff line number Diff line
@@ -88,13 +88,30 @@ CFLAGS-$(CONFIG_PPC64) += $(call cc-option,-mcmodel=medium,-mminimal-toc) 
CFLAGS-$(CONFIG_PPC64)	+= $(call cc-option,-mno-pointers-to-nested-functions)

CFLAGS-$(CONFIG_PPC32)	:= -ffixed-r2 -mmultiple



ifeq ($(CONFIG_PPC_BOOK3S_64),y)

CFLAGS-$(CONFIG_GENERIC_CPU) += $(call cc-option,-mtune=power7,-mtune=power4)

else

CFLAGS-$(CONFIG_GENERIC_CPU) += -mcpu=powerpc64

endif



CFLAGS-$(CONFIG_CELL_CPU) += $(call cc-option,-mcpu=cell)

CFLAGS-$(CONFIG_POWER4_CPU) += $(call cc-option,-mcpu=power4)

CFLAGS-$(CONFIG_POWER5_CPU) += $(call cc-option,-mcpu=power5)

CFLAGS-$(CONFIG_POWER6_CPU) += $(call cc-option,-mcpu=power6)

CFLAGS-$(CONFIG_POWER7_CPU) += $(call cc-option,-mcpu=power7)



E5500_CPU := $(call cc-option,-mcpu=e500mc64,-mcpu=powerpc64)

CFLAGS-$(CONFIG_E5500_CPU) += $(E5500_CPU)

CFLAGS-$(CONFIG_E6500_CPU) += $(call cc-option,-mcpu=e6500,$(E5500_CPU))



ifeq ($(CONFIG_PPC32),y)

ifeq ($(CONFIG_PPC_E500MC),y)

CFLAGS-y += $(call cc-option,-mcpu=e500mc,-mcpu=powerpc)

else

CFLAGS-$(CONFIG_E500) += $(call cc-option,-mcpu=8540 -msoft-float,-mcpu=powerpc)

endif

endif



CFLAGS-$(CONFIG_TUNE_CELL) += $(call cc-option,-mtune=cell)



KBUILD_CPPFLAGS	+= -Iarch/$(ARCH)
@@ -139,7 +156,6 @@ endif 


cpu-as-$(CONFIG_4xx)		+= -Wa,-m405

cpu-as-$(CONFIG_ALTIVEC)	+= -Wa,-maltivec

cpu-as-$(CONFIG_E500)		+= -Wa,-me500

cpu-as-$(CONFIG_E200)		+= -Wa,-me200



KBUILD_AFLAGS += $(cpu-as-y)