Loading arch/arm/boot/dts/qcom/msmtitanium-cdp.dtsi +1 −1 Original line number Diff line number Diff line Loading @@ -16,7 +16,7 @@ &soc { }; &blsp1_uart2 { &blsp1_uart0 { status = "ok"; pinctrl-names = "default"; pinctrl-0 = <&uart_console_active>; Loading arch/arm/boot/dts/qcom/msmtitanium-mtp.dtsi +1 −1 Original line number Diff line number Diff line Loading @@ -16,7 +16,7 @@ &soc { }; &blsp1_uart2 { &blsp1_uart0 { status = "ok"; pinctrl-names = "default"; pinctrl-0 = <&uart_console_active>; Loading arch/arm/boot/dts/qcom/msmtitanium-rumi.dts +1 −1 Original line number Diff line number Diff line Loading @@ -27,7 +27,7 @@ }; }; &blsp1_uart2 { &blsp1_uart0 { status = "ok"; pinctrl-names = "default"; pinctrl-0 = <&uart_console_active>; Loading arch/arm/boot/dts/qcom/msmtitanium-sim.dts +1 −1 Original line number Diff line number Diff line Loading @@ -21,7 +21,7 @@ qcom,board-id= <16 0>; }; &blsp1_uart2 { &blsp1_uart0 { status = "ok"; pinctrl-names = "default"; pinctrl-0 = <&uart_console_sleep>; Loading arch/arm/boot/dts/qcom/msmtitanium.dtsi +4 −4 Original line number Diff line number Diff line Loading @@ -456,12 +456,12 @@ }; }; blsp1_uart2: serial@78b0000 { blsp1_uart0: serial@78af000 { compatible = "qcom,msm-lsuart-v14"; reg = <0x78b0000 0x200>; interrupts = <0 108 0>; reg = <0x78af000 0x200>; interrupts = <0 107 0>; status = "disabled"; clocks = <&clock_gcc clk_gcc_blsp1_uart2_apps_clk>, clocks = <&clock_gcc clk_gcc_blsp1_uart1_apps_clk>, <&clock_gcc clk_gcc_blsp1_ahb_clk>; clock-names = "core_clk", "iface_clk"; }; Loading Loading
arch/arm/boot/dts/qcom/msmtitanium-cdp.dtsi +1 −1 Original line number Diff line number Diff line Loading @@ -16,7 +16,7 @@ &soc { }; &blsp1_uart2 { &blsp1_uart0 { status = "ok"; pinctrl-names = "default"; pinctrl-0 = <&uart_console_active>; Loading
arch/arm/boot/dts/qcom/msmtitanium-mtp.dtsi +1 −1 Original line number Diff line number Diff line Loading @@ -16,7 +16,7 @@ &soc { }; &blsp1_uart2 { &blsp1_uart0 { status = "ok"; pinctrl-names = "default"; pinctrl-0 = <&uart_console_active>; Loading
arch/arm/boot/dts/qcom/msmtitanium-rumi.dts +1 −1 Original line number Diff line number Diff line Loading @@ -27,7 +27,7 @@ }; }; &blsp1_uart2 { &blsp1_uart0 { status = "ok"; pinctrl-names = "default"; pinctrl-0 = <&uart_console_active>; Loading
arch/arm/boot/dts/qcom/msmtitanium-sim.dts +1 −1 Original line number Diff line number Diff line Loading @@ -21,7 +21,7 @@ qcom,board-id= <16 0>; }; &blsp1_uart2 { &blsp1_uart0 { status = "ok"; pinctrl-names = "default"; pinctrl-0 = <&uart_console_sleep>; Loading
arch/arm/boot/dts/qcom/msmtitanium.dtsi +4 −4 Original line number Diff line number Diff line Loading @@ -456,12 +456,12 @@ }; }; blsp1_uart2: serial@78b0000 { blsp1_uart0: serial@78af000 { compatible = "qcom,msm-lsuart-v14"; reg = <0x78b0000 0x200>; interrupts = <0 108 0>; reg = <0x78af000 0x200>; interrupts = <0 107 0>; status = "disabled"; clocks = <&clock_gcc clk_gcc_blsp1_uart2_apps_clk>, clocks = <&clock_gcc clk_gcc_blsp1_uart1_apps_clk>, <&clock_gcc clk_gcc_blsp1_ahb_clk>; clock-names = "core_clk", "iface_clk"; }; Loading